diff --git a/alu_16.vhd b/alu_16.vhd index 2248b08..bc083a9 100644 --- a/alu_16.vhd +++ b/alu_16.vhd @@ -94,12 +94,10 @@ Process(CLOCK, RESET) output <= shift_right(input1, to_integer(unsigned(input2))); out_code <= in_code; when LSL => - input1_temp <= std_logic_vector(input1); - output <= signed(shift_left(unsigned(input1_temp), to_integer(unsigned(input2)))); + output <= signed(shift_left(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2)))); out_code <= in_code; when LSR => - input1_temp <= std_logic_vector(input1); - output <= signed(shift_right(unsigned(input1_temp), to_integer(unsigned(input2)))); + output <= signed(shift_right(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2)))); out_code <= in_code; when others => output <= "0000000000000000"; diff --git a/alu_16.vhd.bak b/alu_16.vhd.bak index d7f5618..dbe8b23 100644 --- a/alu_16.vhd.bak +++ b/alu_16.vhd.bak @@ -29,7 +29,7 @@ architecture implementation of alu_16 is CONSTANT ADD : unsigned(3 downto 0) := "0000"; CONSTANT SUB : unsigned(3 downto 0) := "0001"; CONSTANT NOT_IN : unsigned(3 downto 0) := "0010"; -CONSTANT ADD_IN : unsigned(3 downto 0) := "0011"; +CONSTANT AND_IN : unsigned(3 downto 0) := "0011"; CONSTANT NAND_IN : unsigned(3 downto 0) := "0100"; CONSTANT OR_IN : unsigned(3 downto 0) := "0101"; CONSTANT NOR_IN : unsigned(3 downto 0) := "0110"; @@ -94,12 +94,12 @@ Process(CLOCK, RESET) output <= shift_right(input1, to_integer(unsigned(input2))); out_code <= in_code; when LSL => - input1_temp <= std_logic_vector(input1); - output <= signed(shift_left(unsigned(input1_temp), to_integer(unsigned(input2)))); + --input1_temp <= std_logic_vector(input1); + output <= signed(shift_left(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2)))); out_code <= in_code; when LSR => - input1_temp <= std_logic_vector(input1); - output <= signed(shift_right(unsigned(input1_temp), to_integer(unsigned(input2)))); + --input1_temp <= std_logic_vector(input1); + output <= signed(shift_right(unsigned(std_logic_vector(input1)), to_integer(unsigned(input2)))); out_code <= in_code; when others => output <= "0000000000000000"; diff --git a/alu_tb.tcl b/alu_tb.tcl new file mode 100644 index 0000000..ec708f5 --- /dev/null +++ b/alu_tb.tcl @@ -0,0 +1,30 @@ +proc AddWaves {} { + ;#Add waves we're interested in to the Wave window + add wave -position end sim:/alu_tb/opcode_t + add wave -position end sim:/alu_tb/input1_t + add wave -position end sim:/alu_tb/input2_t + add wave -position end sim:/alu_tb/clk + add wave -position end sim:/alu_tb/reset_t + add wave -position end sim:/alu_tb/output_t + add wave -position end sim:/alu_tb/status_t +} + +vlib work + +;# Compile components if any +vcom alu_16.vhd +vcom alu_tb.vhd + +;# Start simulation +vsim alu_tb + +;# Add the waves + +AddWaves + +;# Generate a clock with 1ns period +force -deposit clk 0 0 ns, 1 0.5 ns -repeat 1 ns + + +;# Run for 50 ns +run 50ns \ No newline at end of file diff --git a/alu_tb.vhd b/alu_tb.vhd index 755846a..1957e95 100644 --- a/alu_tb.vhd +++ b/alu_tb.vhd @@ -6,10 +6,10 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity alu_testbed is +entity alu_tb is end entity; -architecture testbed of alu_testbed is +architecture testbed of alu_tb is Component alu_16 is Generic( @@ -31,7 +31,8 @@ end component; CONSTANT DATA_WIDTH : integer := 16; --The input signals with their initial values -Signal clk, reset_t : std_logic := '0'; +Signal clk : std_logic := '0'; +Signal reset_t : std_logic := '0'; Signal input1_t : signed(DATA_WIDTH-1 downto 0) := (others => '0'); Signal input2_t : signed(DATA_WIDTH-1 downto 0) := (others => '0'); @@ -41,7 +42,7 @@ Signal opcode_t : unsigned(3 downto 0); Signal status_t : unsigned(3 downto 0); -- clock input -CONSTANT clk_period : time := 10 ns; +CONSTANT clk_period : time := 1 ns; CONSTANT ADD : unsigned(3 downto 0) := "0000"; CONSTANT SUB : unsigned(3 downto 0) := "0001"; @@ -67,8 +68,7 @@ CONSTANT TEST6_NUM : signed(DATA_WIDTH-1 downto 0) := "0100110011110011"; -- Begin -dut: alu_16 -PORT MAP(opcode_t, input1_t, input2_t, clk, reset_t, output_t, status_t); +dut: alu_16 PORT MAP(OPCODE => opcode_t, DATA0 => input1_t, DATA1 => input2_t, CLOCK => clk, RESET => reset_t, DATA_OUT => output_t, STATUS => status_t); -- process for clock clk_process : Process @@ -80,14 +80,323 @@ Begin end process; -test_alu_process: process +stim_process: process Begin - -- test add and subtract - --REPORT "begin test case with double slash comment"; - --s_input <= test_case_doubleslash(i); - --wait for 1 * clk_period; - --ASSERT(s_output = '0') REPORT "no comment, and input backslash should be output = '0'" SEVERITY ERROR; - --end loop; + + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + + -- test add + REPORT "begin test case for add function"; + opcode_t <= ADD; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "addition failed" SEVERITY ERROR; + ASSERT(status_t = ADD) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST1_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0101011001010100") REPORT "addition failed" SEVERITY ERROR; + ASSERT(status_t = ADD) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST3_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1010100110101010") REPORT "addition failed" SEVERITY ERROR; + ASSERT(status_t = ADD) REPORT "status output incorrect" SEVERITY ERROR; + + --SUB + + REPORT "begin test case for SUB function"; + opcode_t <= SUB; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1010101010101011") REPORT "subtraction failed" SEVERITY ERROR; + ASSERT(status_t = SUB) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST6_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1000001000010011") REPORT "subtraction failed" SEVERITY ERROR; + ASSERT(status_t = SUB) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST3_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0101010001010110") REPORT "subtraction failed" SEVERITY ERROR; + ASSERT(status_t = SUB) REPORT "status output incorrect" SEVERITY ERROR; + + --NOT + + REPORT "begin test case for NOT function"; + opcode_t <= NOT_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST2_NUM) REPORT "NOT failed" SEVERITY ERROR; + ASSERT(status_t = NOT_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST1_NUM) REPORT "NOT failed" SEVERITY ERROR; + ASSERT(status_t = NOT_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST1_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0011000011111001") REPORT "NOT failed" SEVERITY ERROR; + ASSERT(status_t = NOT_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --AND + + REPORT "begin test case for AND function"; + opcode_t <= AND_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000000") REPORT "AND failed" SEVERITY ERROR; + ASSERT(status_t = AND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST2_NUM) REPORT "AND failed" SEVERITY ERROR; + ASSERT(status_t = AND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000110") REPORT "AND failed" SEVERITY ERROR; + ASSERT(status_t = AND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --NAND + + REPORT "begin test case for NAND function"; + opcode_t <= NAND_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "NAND failed" SEVERITY ERROR; + ASSERT(status_t = NAND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST1_NUM) REPORT "NAND failed" SEVERITY ERROR; + ASSERT(status_t = NAND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111001") REPORT "NAND failed" SEVERITY ERROR; + ASSERT(status_t = NAND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --OR + + REPORT "begin test case for OR function"; + opcode_t <= OR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "OR failed" SEVERITY ERROR; + ASSERT(status_t = OR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST2_NUM) REPORT "OR failed" SEVERITY ERROR; + ASSERT(status_t = OR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1100111111111111") REPORT "OR failed" SEVERITY ERROR; + ASSERT(status_t = OR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + + --NOR + + REPORT "begin test case for NOR function"; + opcode_t <= NOR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000000") REPORT "NOR failed" SEVERITY ERROR; + ASSERT(status_t = NOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST1_NUM) REPORT "NOR failed" SEVERITY ERROR; + ASSERT(status_t = NOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0011000000000000") REPORT "NOR failed" SEVERITY ERROR; + ASSERT(status_t = NOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + --XOR + + REPORT "begin test case for XOR function"; + opcode_t <= XOR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "XOR failed" SEVERITY ERROR; + ASSERT(status_t = XOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST6_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1000001111110101") REPORT "XOR failed" SEVERITY ERROR; + ASSERT(status_t = XOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1100111111111001") REPORT "XOR failed" SEVERITY ERROR; + ASSERT(status_t = XOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --XNOR + + REPORT "begin test case for XNOR function"; + opcode_t <= XNOR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000000") REPORT "XNOR failed" SEVERITY ERROR; + ASSERT(status_t = XNOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST6_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0111110000001010") REPORT "XNOR failed" SEVERITY ERROR; + ASSERT(status_t = XNOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0011000000000110") REPORT "XNOR failed" SEVERITY ERROR; + ASSERT(status_t = XNOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --ASL + + REPORT "begin test case for ASL function"; + opcode_t <= ASL; + input1_t <= TEST1_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "1010101010101000") REPORT "ASL failed" SEVERITY ERROR; + ASSERT(status_t = ASL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "1001111000001100") REPORT "ASL failed" SEVERITY ERROR; + ASSERT(status_t = ASL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST3_NUM; + input2_t <= "0000000000000110"; + wait for 1 * clk_period; + ASSERT(output_t = "1100000000000000") REPORT "ASL failed" SEVERITY ERROR; + ASSERT(status_t = ASL) REPORT "status output incorrect" SEVERITY ERROR; + + --ASR + + REPORT "begin test case for ASR function"; + opcode_t <= ASR; + input1_t <= TEST2_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "1111010101010101") REPORT "ASR failed" SEVERITY ERROR; + ASSERT(status_t = ASR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "1110011110000011") REPORT "ASR failed" SEVERITY ERROR; + ASSERT(status_t = ASR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST1_NUM; + input2_t <= "0000000000000110"; + wait for 1 * clk_period; + ASSERT(output_t = "0000000101010101") REPORT "ASR failed" SEVERITY ERROR; + ASSERT(status_t = ASR) REPORT "status output incorrect" SEVERITY ERROR; + + + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + + --LSL + + REPORT "begin test case for LSL function"; + opcode_t <= LSL; + input1_t <= TEST1_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "1010101010101000") REPORT "LSL failed" SEVERITY ERROR; + ASSERT(status_t = LSL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "1001111000001100") REPORT "LSL failed" SEVERITY ERROR; + ASSERT(status_t = LSL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST3_NUM; + input2_t <= "0000000000000111"; + wait for 1 * clk_period; + ASSERT(output_t = "1000000000000000") REPORT "LSL failed" SEVERITY ERROR; + ASSERT(status_t = LSL) REPORT "status output incorrect" SEVERITY ERROR; + + --LSR + + REPORT "begin test case for LSR function"; + opcode_t <= LSR; + input1_t <= TEST1_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "0000101010101010") REPORT "LSR failed" SEVERITY ERROR; + ASSERT(status_t = LSR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST6_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "0010011001111001") REPORT "LSR failed" SEVERITY ERROR; + ASSERT(status_t = LSR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= "0000000000001111"; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000001") REPORT "LSR failed" SEVERITY ERROR; + ASSERT(status_t = LSR) REPORT "status output incorrect" SEVERITY ERROR; + + REPORT "TESTING Complete"; + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + REPORT "RESET Complete"; + + WAIT; end process; diff --git a/alu_tb.vhd.bak b/alu_tb.vhd.bak index 026f246..f14d0d5 100644 --- a/alu_tb.vhd.bak +++ b/alu_tb.vhd.bak @@ -6,10 +6,10 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity alu_testbed is +entity alu_tb is end entity; -architecture testbed of alu_testbed is +architecture testbed of alu_tb is Component alu_16 is Generic( @@ -31,7 +31,8 @@ end component; CONSTANT DATA_WIDTH : integer := 16; --The input signals with their initial values -Signal clk, reset_t : std_logic := '0'; +Signal clk : std_logic := '0'; +Signal reset_t : std_logic := '0'; Signal input1_t : signed(DATA_WIDTH-1 downto 0) := (others => '0'); Signal input2_t : signed(DATA_WIDTH-1 downto 0) := (others => '0'); @@ -41,7 +42,7 @@ Signal opcode_t : unsigned(3 downto 0); Signal status_t : unsigned(3 downto 0); -- clock input -CONSTANT clk_period : time := 10 ns; +CONSTANT clk_period : time := 1 ns; CONSTANT ADD : unsigned(3 downto 0) := "0000"; CONSTANT SUB : unsigned(3 downto 0) := "0001"; @@ -67,8 +68,7 @@ CONSTANT TEST6_NUM : signed(DATA_WIDTH-1 downto 0) := "0100110011110011"; -- Begin -dut: alu_16 -PORT MAP(opcode_t, input1_t, input2_t, clk, reset_t, output_t, status_t); +dut: alu_16 PORT MAP(OPCODE => opcode_t, DATA0 => input1_t, DATA1 => input2_t, CLOCK => clk, RESET => reset_t, DATA_OUT => output_t, STATUS => status_t); -- process for clock clk_process : Process @@ -80,14 +80,323 @@ Begin end process; -test_alu_process: process +stim_process: process Begin - -- test add and subtract - REPORT "begin test case with double slash comment"; - s_input <= test_case_doubleslash(i); + + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + + -- test add + REPORT "begin test case for add function"; + opcode_t <= ADD; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "addition failed" SEVERITY ERROR; + ASSERT(status_t = ADD) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST1_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0101011001010100") REPORT "addition failed" SEVERITY ERROR; + ASSERT(status_t = ADD) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST3_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1010100110101010") REPORT "addition failed" SEVERITY ERROR; + ASSERT(status_t = ADD) REPORT "status output incorrect" SEVERITY ERROR; + + --SUB + + REPORT "begin test case for SUB function"; + opcode_t <= SUB; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1010101010101011") REPORT "subtraction failed" SEVERITY ERROR; + ASSERT(status_t = SUB) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST6_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1000001000010011") REPORT "subtraction failed" SEVERITY ERROR; + ASSERT(status_t = SUB) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST3_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0101010001010110") REPORT "subtraction failed" SEVERITY ERROR; + ASSERT(status_t = SUB) REPORT "status output incorrect" SEVERITY ERROR; + + --NOT + + REPORT "begin test case for NOT function"; + opcode_t <= NOT_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST2_NUM) REPORT "NOT failed" SEVERITY ERROR; + ASSERT(status_t = NOT_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST1_NUM) REPORT "NOT failed" SEVERITY ERROR; + ASSERT(status_t = NOT_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST1_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0011000011111001") REPORT "NOT failed" SEVERITY ERROR; + ASSERT(status_t = NOT_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --AND + + REPORT "begin test case for AND function"; + opcode_t <= AND_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000000") REPORT "AND failed" SEVERITY ERROR; + ASSERT(status_t = AND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST2_NUM) REPORT "AND failed" SEVERITY ERROR; + ASSERT(status_t = AND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000110") REPORT "AND failed" SEVERITY ERROR; + ASSERT(status_t = AND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --NAND + + REPORT "begin test case for NAND function"; + opcode_t <= NAND_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "NAND failed" SEVERITY ERROR; + ASSERT(status_t = NAND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST1_NUM) REPORT "NAND failed" SEVERITY ERROR; + ASSERT(status_t = NAND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111001") REPORT "NAND failed" SEVERITY ERROR; + ASSERT(status_t = NAND_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --OR + + REPORT "begin test case for OR function"; + opcode_t <= OR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "OR failed" SEVERITY ERROR; + ASSERT(status_t = OR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST2_NUM) REPORT "OR failed" SEVERITY ERROR; + ASSERT(status_t = OR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1100111111111111") REPORT "OR failed" SEVERITY ERROR; + ASSERT(status_t = OR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + + --NOR + + REPORT "begin test case for NOR function"; + opcode_t <= NOR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000000") REPORT "NOR failed" SEVERITY ERROR; + ASSERT(status_t = NOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + + input1_t <= TEST2_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = TEST1_NUM) REPORT "NOR failed" SEVERITY ERROR; + ASSERT(status_t = NOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0011000000000000") REPORT "NOR failed" SEVERITY ERROR; + ASSERT(status_t = NOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + reset_t <= '1'; wait for 1 * clk_period; - ASSERT(s_output = '0') REPORT "no comment, and input backslash should be output = '0'" SEVERITY ERROR; - end loop; + reset_t <= '0'; + wait for 1 * clk_period; + --XOR + + REPORT "begin test case for XOR function"; + opcode_t <= XOR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1111111111111111") REPORT "XOR failed" SEVERITY ERROR; + ASSERT(status_t = XOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST6_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1000001111110101") REPORT "XOR failed" SEVERITY ERROR; + ASSERT(status_t = XOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "1100111111111001") REPORT "XOR failed" SEVERITY ERROR; + ASSERT(status_t = XOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --XNOR + + REPORT "begin test case for XNOR function"; + opcode_t <= XNOR_IN; + input1_t <= TEST1_NUM; + input2_t <= TEST2_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000000") REPORT "XNOR failed" SEVERITY ERROR; + ASSERT(status_t = XNOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST6_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0111110000001010") REPORT "XNOR failed" SEVERITY ERROR; + ASSERT(status_t = XNOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= TEST4_NUM; + wait for 1 * clk_period; + ASSERT(output_t = "0011000000000110") REPORT "XNOR failed" SEVERITY ERROR; + ASSERT(status_t = XNOR_IN) REPORT "status output incorrect" SEVERITY ERROR; + + --ASL + + REPORT "begin test case for ASL function"; + opcode_t <= ASL; + input1_t <= TEST1_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "1010101010101000") REPORT "ASL failed" SEVERITY ERROR; + ASSERT(status_t = ASL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "1001111000001100") REPORT "ASL failed" SEVERITY ERROR; + ASSERT(status_t = ASL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST3_NUM; + input2_t <= "0000000000000110"; + wait for 1 * clk_period; + ASSERT(output_t = "1100000000000000") REPORT "ASL failed" SEVERITY ERROR; + ASSERT(status_t = ASL) REPORT "status output incorrect" SEVERITY ERROR; + + --ASR + + REPORT "begin test case for ASR function"; + opcode_t <= ASR; + input1_t <= TEST2_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "1111010101010101") REPORT "ASR failed" SEVERITY ERROR; + ASSERT(status_t = ASR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "1110011110000011") REPORT "ASR failed" SEVERITY ERROR; + ASSERT(status_t = ASR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST1_NUM; + input2_t <= "0000000000000110"; + wait for 1 * clk_period; + ASSERT(output_t = "0000000101010101") REPORT "ASR failed" SEVERITY ERROR; + ASSERT(status_t = ASR) REPORT "status output incorrect" SEVERITY ERROR; + + + reset_t <= '1'; + wait for 1 * clk_period; + reset_t <= '0'; + wait for 1 * clk_period; + + --LSL + + REPORT "begin test case for LSL function"; + opcode_t <= LSL; + input1_t <= TEST1_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "1010101010101000") REPORT "LSL failed" SEVERITY ERROR; + ASSERT(status_t = LSL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST5_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "1001111000001100") REPORT "LSL failed" SEVERITY ERROR; + ASSERT(status_t = LSL) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST3_NUM; + input2_t <= "0000000000000111"; + wait for 1 * clk_period; + ASSERT(output_t = "1000000000000000") REPORT "LSL failed" SEVERITY ERROR; + ASSERT(status_t = LSL) REPORT "status output incorrect" SEVERITY ERROR; + + --LSR + +CONSTANT TEST1_NUM : signed(DATA_WIDTH-1 downto 0) := "0101010101010101"; -- +CONSTANT TEST2_NUM : signed(DATA_WIDTH-1 downto 0) := "1010101010101010"; -- +CONSTANT TEST3_NUM : signed(DATA_WIDTH-1 downto 0) := "1111111100000000"; -- +CONSTANT TEST4_NUM : signed(DATA_WIDTH-1 downto 0) := "0000000011111111"; -- +CONSTANT TEST5_NUM : signed(DATA_WIDTH-1 downto 0) := "1100111100000110"; -- +CONSTANT TEST6_NUM : signed(DATA_WIDTH-1 downto 0) := "0100110011110011"; -- + + REPORT "begin test case for LSR function"; + opcode_t <= LSR; + input1_t <= TEST1_NUM; + input2_t <= "0000000000000011"; + wait for 1 * clk_period; + ASSERT(output_t = "0000101010101010") REPORT "LSR failed" SEVERITY ERROR; + ASSERT(status_t = LSR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST6_NUM; + input2_t <= "0000000000000001"; + wait for 1 * clk_period; + ASSERT(output_t = "0010011001111001") REPORT "LSR failed" SEVERITY ERROR; + ASSERT(status_t = LSR) REPORT "status output incorrect" SEVERITY ERROR; + + input1_t <= TEST2_NUM; + input2_t <= "0000000000001111"; + wait for 1 * clk_period; + ASSERT(output_t = "0000000000000001") REPORT "LSR failed" SEVERITY ERROR; + ASSERT(status_t = LSR) REPORT "status output incorrect" SEVERITY ERROR; + + WAIT; end process; diff --git a/transcript b/transcript index 52d0913..91fe335 100644 --- a/transcript +++ b/transcript @@ -1,231 +1,1434 @@ # Reading C:/altera/15.0/modelsim_ase/tcl/vsim/pref.tcl # OpenFile C:/Users/scarte9/ECSE487-ALU/alu_16.vhd -vlib work -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd +source alu_tb.tcl # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:13:31 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd +# Start time: 15:27:15 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity alu_16 # -- Compiling architecture implementation of alu_16 -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(72): (vcom-1136) Unknown identifier "AND_IN". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(72): Choice in CASE statement alternative must be locally static. -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_16.vhd(112): VHDL Compiler exiting -# End time: 11:13:31 on Jan 29,2016, Elapsed time: 0:00:00 +# End time: 15:27:15 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:27:15 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:27:16 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim -gui C:\Users\scarte9\ECSE487-ALU\alu_16.vhd +# Start time: 15:27:16 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:29:31 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:29:31 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:29:31 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:29:31 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:29:31 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 4 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 6 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:31:29 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:31:29 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:31:29 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:31:29 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:31:29 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 4 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 6 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:37:01 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:37:01 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:37:01 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:37:01 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:37:01 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 4 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 6 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:38:31 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:38:31 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:38:31 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:38:31 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:38:31 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 4 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:40:33 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:40:34 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:40:34 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:40:34 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:40:34 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:44:50 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:44:51 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:44:51 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:44:51 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:44:51 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 4 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:47:52 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:47:52 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:47:52 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:47:53 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:47:53 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Error: subtraction failed +# Time: 4 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:49:35 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:49:35 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:49:35 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:49:36 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:49:36 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for subtract function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:52:56 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 15:52:57 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 15:52:57 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 15:52:57 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 15:52:57 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +quit -sim +# Load canceled +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:00:12 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:00:12 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:00:12 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:00:13 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:00:13 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 12 ns Iteration: 0 Instance: /alu_tb +restart -f +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:00:43 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:00:43 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:00:43 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:00:43 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:00:43 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:03:12 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:03:12 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:03:12 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:03:12 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:03:12 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Error: NAND failed +# Time: 14 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:04:20 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:04:20 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:04:20 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:04:21 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:04:21 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Error: NAND failed +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Error: NAND failed +# Time: 15 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:05:46 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:05:46 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:05:46 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# ** Error: alu_tb.vhd(185): near ") REPORT ": expecting ')' +# ** Error: alu_tb.vhd(185): near " SEVERITY ERROR;": (vcom-1203) String literal is not terminated with the " character. +# ** Error: alu_tb.vhd(200): VHDL Compiler exiting +# End time: 16:05:46 on Jan 31,2016, Elapsed time: 0:00:00 # Errors: 3, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd -# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:13:51 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd -# -- Loading package STANDARD -# -- Loading package TEXTIO -# -- Loading package std_logic_1164 -# -- Loading package NUMERIC_STD -# -- Compiling entity alu_16 -# -- Compiling architecture implementation of alu_16 -# End time: 11:13:51 on Jan 29,2016, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd -# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:13:54 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd -# -- Loading package STANDARD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(15): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(16): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(17): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(19): (vcom-1136) Unknown identifier "std_logic". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(20): (vcom-1136) Unknown identifier "std_logic". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(22): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(23): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(30): (vcom-1136) Unknown identifier "std_logic". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(30): Enumeration literal '0' is not of type (error). -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(32): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(33): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(34): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(36): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(37): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(42): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(43): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(44): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(45): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(46): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(47): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(48): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(49): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(50): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(51): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(52): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(53): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(54): (vcom-1136) Unknown identifier "unsigned". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(56): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(57): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(58): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(59): (vcom-1136) Unknown identifier "signed". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(63): VHDL Compiler exiting -# End time: 11:13:54 on Jan 29,2016, Elapsed time: 0:00:00 -# Errors: 32, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd -# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:14:10 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd -# -- Loading package STANDARD +# C:/altera/15.0/modelsim_ase/win32aloem/vcom failed. +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:06:00 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:06:00 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:06:00 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:06:01 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:06:01 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 12 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:08:25 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:08:25 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:08:25 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:08:25 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:08:25 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 15 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:10:02 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:10:03 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:10:03 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:10:03 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:10:03 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 15 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 18 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:15:25 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:15:25 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:15:25 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:15:25 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:15:25 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 15 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 18 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 21 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:18:28 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:18:28 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:18:28 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:18:29 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:18:29 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 0 ps Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 15 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 18 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 21 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 24 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:20:56 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:20:56 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:20:56 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# End time: 11:14:10 on Jan 29,2016, Elapsed time: 0:00:00 +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:20:56 on Jan 31,2016, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# vsim +# Start time: 16:20:56 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 1 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 3 ns Iteration: 0 Instance: /alu_tb +# ** Error: addition failed +# Time: 4 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 4 ns Iteration: 0 Instance: /alu_tb +# ** Error: subtraction failed +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Error: subtraction failed +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 6 ns Iteration: 0 Instance: /alu_tb +# ** Error: subtraction failed +# Time: 7 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 7 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 7 ns Iteration: 0 Instance: /alu_tb +# ** Error: NOT failed +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Error: NOT failed +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 9 ns Iteration: 0 Instance: /alu_tb +# ** Error: NOT failed +# Time: 10 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 10 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 10 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Error: AND failed +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 12 ns Iteration: 0 Instance: /alu_tb +# ** Error: AND failed +# Time: 13 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 13 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 13 ns Iteration: 0 Instance: /alu_tb +# ** Error: NAND failed +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Error: NAND failed +# Time: 15 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 15 ns Iteration: 0 Instance: /alu_tb +# ** Error: NAND failed +# Time: 16 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 16 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 16 ns Iteration: 0 Instance: /alu_tb +# ** Error: OR failed +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Error: OR failed +# Time: 18 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 18 ns Iteration: 0 Instance: /alu_tb +# ** Error: OR failed +# Time: 19 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 19 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 19 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Error: NOR failed +# Time: 22 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 22 ns Iteration: 0 Instance: /alu_tb +# ** Error: NOR failed +# Time: 23 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 23 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 24 ns Iteration: 0 Instance: /alu_tb +# ** Error: XOR failed +# Time: 25 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 25 ns Iteration: 0 Instance: /alu_tb +# ** Error: XOR failed +# Time: 26 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 26 ns Iteration: 0 Instance: /alu_tb +# ** Error: XOR failed +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 28 ns Iteration: 0 Instance: /alu_tb +# ** Error: XNOR failed +# Time: 29 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 29 ns Iteration: 0 Instance: /alu_tb +# ** Error: XNOR failed +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Error: status output incorrect +# Time: 30 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:14:11 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# Start time: 16:21:48 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# End time: 11:14:12 on Jan 29,2016, Elapsed time: 0:00:01 +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:21:48 on Jan 31,2016, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:20:45 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd -# -- Loading package STANDARD -# -- Loading package TEXTIO -# -- Loading package std_logic_1164 -# -- Loading package NUMERIC_STD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(71): (vcom-1136) Unknown identifier "input1". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(71): (vcom-1136) Unknown identifier "input2". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(87): Illegal target for signal assignment. -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(87): (vcom-1136) Unknown identifier "s_input". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(89): (vcom-1136) Unknown identifier "s_output". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(89): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(90): near "loop": expecting PROCESS -# End time: 11:20:45 on Jan 29,2016, Elapsed time: 0:00:00 -# Errors: 7, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd +# Start time: 16:21:48 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:21:49 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:21:49 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:20:47 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_16.vhd +# Start time: 16:25:55 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity alu_16 # -- Compiling architecture implementation of alu_16 -# End time: 11:20:48 on Jan 29,2016, Elapsed time: 0:00:01 +# End time: 16:25:56 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:25:56 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:25:56 on Jan 31,2016, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# vsim +# Start time: 16:25:56 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASL function +# Time: 33 ns Iteration: 0 Instance: /alu_tb +# ** Error: ASL failed +# Time: 34 ns Iteration: 0 Instance: /alu_tb +# ** Error: ASL failed +# Time: 36 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:20:52 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# Start time: 16:28:36 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(71): (vcom-1136) Unknown identifier "input1". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(71): (vcom-1136) Unknown identifier "input2". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(87): Illegal target for signal assignment. -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(87): (vcom-1136) Unknown identifier "s_input". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(89): (vcom-1136) Unknown identifier "s_output". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(89): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(90): near "loop": expecting PROCESS -# End time: 11:20:52 on Jan 29,2016, Elapsed time: 0:00:00 -# Errors: 7, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:28:36 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:21:45 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# Start time: 16:28:36 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(87): Illegal target for signal assignment. -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(87): (vcom-1136) Unknown identifier "s_input". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(89): (vcom-1136) Unknown identifier "s_output". -# -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(89): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN. -# ** Error: C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(90): near "loop": expecting PROCESS -# End time: 11:21:45 on Jan 29,2016, Elapsed time: 0:00:00 -# Errors: 5, Warnings: 0 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:28:37 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:28:37 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASL function +# Time: 33 ns Iteration: 0 Instance: /alu_tb +# ** Error: ASL failed +# Time: 36 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:22:05 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# Start time: 16:30:07 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# ** Warning: [2] C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(91): (vcom-1090) Possible infinite loop: Process contains no WAIT statement. -# -# End time: 11:22:06 on Jan 29,2016, Elapsed time: 0:00:01 -# Errors: 0, Warnings: 1 -vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:30:08 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 # Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 -# Start time: 11:22:09 on Jan 29,2016 -# vcom -reportprogress 300 -work work C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +# Start time: 16:30:08 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD -# -- Compiling entity alu_testbed -# -- Compiling architecture testbed of alu_testbed -# ** Warning: [2] C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd(91): (vcom-1090) Possible infinite loop: Process contains no WAIT statement. -# -# End time: 11:22:09 on Jan 29,2016, Elapsed time: 0:00:00 -# Errors: 0, Warnings: 1 +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:30:08 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:30:08 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASL function +# Time: 33 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:41:09 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:41:09 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:41:09 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# ** Error: alu_tb.vhd(292): near "1010101010101010": (vcom-119) Integer value exceeds INTEGER'high. +# ** Error: alu_tb.vhd(292): near "1010101010101010": syntax error +# ** Error: alu_tb.vhd(352): VHDL Compiler exiting +# End time: 16:41:09 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 3, Warnings: 0 +# C:/altera/15.0/modelsim_ase/win32aloem/vcom failed. +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:41:22 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:41:23 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:41:23 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:41:23 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:41:23 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASL function +# Time: 33 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASR function +# Time: 36 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:44:25 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:44:25 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:44:25 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:44:25 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:44:25 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASL function +# Time: 33 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASR function +# Time: 36 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for LSL function +# Time: 41 ns Iteration: 0 Instance: /alu_tb +# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE +# Time: 42 ns Iteration: 0 Instance: /alu_tb +# ** Error: LSL failed +# Time: 42 ns Iteration: 0 Instance: /alu_tb +# ** Error: LSL failed +# Time: 43 ns Iteration: 0 Instance: /alu_tb +# ** Error: LSL failed +# Time: 44 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:45:41 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:45:42 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:45:42 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:45:42 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:45:42 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASL function +# Time: 33 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASR function +# Time: 36 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for LSL function +# Time: 41 ns Iteration: 0 Instance: /alu_tb +quit -sim +source alu_tb.tcl +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:49:10 on Jan 31,2016 +# vcom -reportprogress 300 alu_16.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_16 +# -- Compiling architecture implementation of alu_16 +# End time: 16:49:11 on Jan 31,2016, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct 7 2014 +# Start time: 16:49:11 on Jan 31,2016 +# vcom -reportprogress 300 alu_tb.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Compiling entity alu_tb +# -- Compiling architecture testbed of alu_tb +# End time: 16:49:11 on Jan 31,2016, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim +# Start time: 16:49:11 on Jan 31,2016 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading work.alu_tb(testbed) +# Loading work.alu_16(implementation) +# ** Note: begin test case for add function +# Time: 2 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for SUB function +# Time: 5 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOT function +# Time: 8 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for AND function +# Time: 11 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NAND function +# Time: 14 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for OR function +# Time: 17 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for NOR function +# Time: 20 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XOR function +# Time: 27 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for XNOR function +# Time: 30 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASL function +# Time: 33 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for ASR function +# Time: 36 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for LSL function +# Time: 41 ns Iteration: 0 Instance: /alu_tb +# ** Note: begin test case for LSR function +# Time: 44 ns Iteration: 0 Instance: /alu_tb +# ** Note: TESTING Complete +# Time: 47 ns Iteration: 0 Instance: /alu_tb +# ** Note: RESET Complete +# Time: 49 ns Iteration: 0 Instance: /alu_tb +# WARNING: No extended dataflow license exists +quit -sim diff --git a/vsim.wlf b/vsim.wlf new file mode 100644 index 0000000..2c1beb4 Binary files /dev/null and b/vsim.wlf differ diff --git a/work/_info b/work/_info index 2cc1eaa..53054de 100644 --- a/work/_info +++ b/work/_info @@ -9,36 +9,35 @@ z2 cModel Technology Z0 dC:/Users/scarte9/ECSE487-ALU Ealu_16 -Z1 w1454084025 +Z1 w1454276784 Z2 DPx4 ieee 11 numeric_std 0 22 :ASDNFgHXf_ih3J@9F3Ze1 Z3 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 Z4 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 R0 -Z5 8C:/Users/scarte9/ECSE487-ALU/alu_16.vhd -Z6 FC:/Users/scarte9/ECSE487-ALU/alu_16.vhd +Z5 8alu_16.vhd +Z6 Falu_16.vhd l0 L10 -V4`L[doCoj0zFFee4gB0 R7 32 R8 @@ -48,45 +47,81 @@ R10 R11 !i113 1 R12 -R13 +Ealu_tb +Z13 w1454276947 +R2 +R3 +R4 +R0 +Z14 8alu_tb.vhd +Z15 Falu_tb.vhd +l0 +L9 +VnFci`<6F?:[Hg=dJ6lR0 +R7 +32 +R8 +!i10b 1 +R16 +R17 +R18 +!i113 1 +R12 Ealu_testbed -Z14 w1454084524 +Z20 w1454271521 R2 R3 R4 R0 -Z15 8C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd -Z16 FC:/Users/scarte9/ECSE487-ALU/alu_tb.vhd +R14 +R15 l0 L9 -V^T01zU@m0mV>9[Y8LTMRZ1 +V]mEFhNP^aWT?RIf1Dml_b2 !s100 QbMF=m9IU6g45:_SmU9lS2 R7 32 -Z17 !s110 1454084529 +Z21 !s110 1454271721 !i10b 1 -Z18 !s108 1454084529.415000 -Z19 !s90 -reportprogress|300|-work|work|C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd| -Z20 !s107 C:/Users/scarte9/ECSE487-ALU/alu_tb.vhd| +Z22 !s108 1454271721.824000 +R17 +R18 !i113 1 R12 -R13 Atestbed R2 R3 R4 -Z21 DEx4 work 11 alu_testbed 0 22 ^T01zU@m0mV>9[Y8LTMRZ1 -l69 +DEx4 work 11 alu_testbed 0 22 ]mEFhNP^aWT?RIf1Dml_b2 +l70 L12 -Z22 V1l0`?LQ0K>@WMnI503`z@0 -Z23 !s100 @Ro:[E7>V