counter_tb.vcd

$date
	Sat Apr 29 09:34:13 2017
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module counter_tb $end
$var wire 2 ! out [1:0] $end
$var reg 1 " clock $end
$var reg 1 # enable $end
$var reg 1 $ reset $end
$scope module top $end
$var wire 1 " clock $end
$var wire 1 # enable $end
$var wire 1 $ reset $end
$var reg 2 % out [1:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx %
0$
0#
1"
bx !
$end
#1
0"
1$
#2
b0 !
b0 %
1"
#3
0"
0$
#4
1"
#5
0"
1#
#6
b1 !
b1 %
1"
#7
0"
#8
b10 !
b10 %
1"
#9
0"
#10
b11 !
b11 %
1"
#11
0"
#12
b0 !
b0 %
1"
#13
0"
#14
b1 !
b1 %
1"
#15
0"
#16
b10 !
b10 %
1"
#17
0"
#18
b11 !
b11 %
1"
#19
0"
#20
b0 !
b0 %
1"
#21
0"
#22
b1 !
b1 %
1"
#23
0"
#24
b10 !
b10 %
1"
#25
0"
0#
#26
1"