From b59de006d5cfb981139a35d4cb0e8971b93ca33c Mon Sep 17 00:00:00 2001 From: sebanc Date: Mon, 28 Nov 2022 07:55:31 +0100 Subject: [PATCH] Changelog: - Update kernels to r109 --- kernel-patches/4.19/chromeos/lsm_shmem.patch | 13 +- kernel-patches/5.15/base/base.patch | 673 ------------------ .../chromebook-5.4/chromeos/lsm_shmem.patch | 13 +- .../macbook/chromeos/lsm_shmem.patch | 13 +- prepare_kernels.sh | 2 +- 5 files changed, 19 insertions(+), 695 deletions(-) diff --git a/kernel-patches/4.19/chromeos/lsm_shmem.patch b/kernel-patches/4.19/chromeos/lsm_shmem.patch index cad40a097..2967cf81b 100644 --- a/kernel-patches/4.19/chromeos/lsm_shmem.patch +++ b/kernel-patches/4.19/chromeos/lsm_shmem.patch @@ -1,11 +1,10 @@ --- ./security/chromiumos/lsm.c 2022-09-28 07:26:42.949182359 +0200 +++ ./security/chromiumos/lsm.c 2022-09-28 07:29:28.984937913 +0200 -@@ -217,7 +217,7 @@ +@@ -217,6 +217,7 @@ + static int chromiumos_bprm_creds_for_exec(struct linux_binprm *bprm) + { struct file *file = bprm->file; ++ return 0; - if (shmem_file(file)) -- return -EACCES; -+ return 0; - - return 0; - } + if (shmem_file(file)) { + char *cmdline = printable_cmdline(current); diff --git a/kernel-patches/5.15/base/base.patch b/kernel-patches/5.15/base/base.patch index c29b05d5d..f72a49e35 100644 --- a/kernel-patches/5.15/base/base.patch +++ b/kernel-patches/5.15/base/base.patch @@ -8226,14 +8226,6 @@ diff -ruN a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig config DRM_LONTIUM_LT8912B tristate "Lontium LT8912B DSI/HDMI bridge" depends on OF -@@ -182,6 +189,7 @@ - config DRM_PARADE_PS8640 - tristate "Parade PS8640 MIPI DSI to eDP Converter" - depends on OF -+ select DRM_DP_AUX_BUS - select DRM_KMS_HELPER - select DRM_MIPI_DSI - select DRM_PANEL diff -ruN a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile --- a/drivers/gpu/drm/bridge/Makefile 2021-12-08 09:04:57.000000000 +0100 +++ b/drivers/gpu/drm/bridge/Makefile 2021-12-23 08:35:26.000000000 +0100 @@ -8245,671 +8237,6 @@ diff -ruN a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile obj-$(CONFIG_DRM_LONTIUM_LT8912B) += lontium-lt8912b.o obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o -diff -ruN a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c ---- a/drivers/gpu/drm/bridge/parade-ps8640.c 2021-12-08 09:04:57.000000000 +0100 -+++ b/drivers/gpu/drm/bridge/parade-ps8640.c 2021-12-23 08:35:26.000000000 +0100 -@@ -9,25 +9,60 @@ - #include - #include - #include -+#include -+#include - #include - - #include -+#include -+#include - #include - #include - #include - #include - -+#define PAGE0_AUXCH_CFG3 0x76 -+#define AUXCH_CFG3_RESET 0xff -+#define PAGE0_SWAUX_ADDR_7_0 0x7d -+#define PAGE0_SWAUX_ADDR_15_8 0x7e -+#define PAGE0_SWAUX_ADDR_23_16 0x7f -+#define SWAUX_ADDR_MASK GENMASK(19, 0) -+#define PAGE0_SWAUX_LENGTH 0x80 -+#define SWAUX_LENGTH_MASK GENMASK(3, 0) -+#define SWAUX_NO_PAYLOAD BIT(7) -+#define PAGE0_SWAUX_WDATA 0x81 -+#define PAGE0_SWAUX_RDATA 0x82 -+#define PAGE0_SWAUX_CTRL 0x83 -+#define SWAUX_SEND BIT(0) -+#define PAGE0_SWAUX_STATUS 0x84 -+#define SWAUX_M_MASK GENMASK(4, 0) -+#define SWAUX_STATUS_MASK GENMASK(7, 5) -+#define SWAUX_STATUS_NACK (0x1 << 5) -+#define SWAUX_STATUS_DEFER (0x2 << 5) -+#define SWAUX_STATUS_ACKM (0x3 << 5) -+#define SWAUX_STATUS_INVALID (0x4 << 5) -+#define SWAUX_STATUS_I2C_NACK (0x5 << 5) -+#define SWAUX_STATUS_I2C_DEFER (0x6 << 5) -+#define SWAUX_STATUS_TIMEOUT (0x7 << 5) -+ - #define PAGE2_GPIO_H 0xa7 --#define PS_GPIO9 BIT(1) -+#define PS_GPIO9 BIT(1) - #define PAGE2_I2C_BYPASS 0xea --#define I2C_BYPASS_EN 0xd0 -+#define I2C_BYPASS_EN 0xd0 - #define PAGE2_MCS_EN 0xf3 --#define MCS_EN BIT(0) -+#define MCS_EN BIT(0) -+ - #define PAGE3_SET_ADD 0xfe --#define VDO_CTL_ADD 0x13 --#define VDO_DIS 0x18 --#define VDO_EN 0x1c --#define DP_NUM_LANES 4 -+#define VDO_CTL_ADD 0x13 -+#define VDO_DIS 0x18 -+#define VDO_EN 0x1c -+ -+#define NUM_MIPI_LANES 4 -+ -+#define COMMON_PS8640_REGMAP_CONFIG \ -+ .reg_bits = 8, \ -+ .val_bits = 8, \ -+ .cache_type = REGCACHE_NONE - - /* - * PS8640 uses multiple addresses: -@@ -60,12 +95,49 @@ - struct ps8640 { - struct drm_bridge bridge; - struct drm_bridge *panel_bridge; -+ struct drm_dp_aux aux; - struct mipi_dsi_device *dsi; - struct i2c_client *page[MAX_DEVS]; -+ struct regmap *regmap[MAX_DEVS]; - struct regulator_bulk_data supplies[2]; - struct gpio_desc *gpio_reset; - struct gpio_desc *gpio_powerdown; -- bool powered; -+ bool pre_enabled; -+}; -+ -+static const struct regmap_config ps8640_regmap_config[] = { -+ [PAGE0_DP_CNTL] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0xbf, -+ }, -+ [PAGE1_VDO_BDG] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0xff, -+ }, -+ [PAGE2_TOP_CNTL] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0xff, -+ }, -+ [PAGE3_DSI_CNTL1] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0xff, -+ }, -+ [PAGE4_MIPI_PHY] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0xff, -+ }, -+ [PAGE5_VPLL] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0x7f, -+ }, -+ [PAGE6_DSI_CNTL2] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0xff, -+ }, -+ [PAGE7_SPI_CNTL] = { -+ COMMON_PS8640_REGMAP_CONFIG, -+ .max_register = 0xff, -+ }, - }; - - static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e) -@@ -73,140 +145,298 @@ - return container_of(e, struct ps8640, bridge); - } - --static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, -- const enum ps8640_vdo_control ctrl) -+static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux) - { -- struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1]; -- u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; -+ return container_of(aux, struct ps8640, aux); -+} -+ -+static bool ps8640_of_panel_on_aux_bus(struct device *dev) -+{ -+ struct device_node *bus, *panel; -+ -+ bus = of_get_child_by_name(dev->of_node, "aux-bus"); -+ if (!bus) -+ return false; -+ -+ panel = of_get_child_by_name(bus, "panel"); -+ of_node_put(bus); -+ if (!panel) -+ return false; -+ of_node_put(panel); -+ -+ return true; -+} -+ -+static int ps8640_ensure_hpd(struct ps8640 *ps_bridge) -+{ -+ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; -+ struct device *dev = &ps_bridge->page[PAGE2_TOP_CNTL]->dev; -+ int status; - int ret; - -- ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD, -- sizeof(vdo_ctrl_buf), -- vdo_ctrl_buf); -- if (ret < 0) { -- DRM_ERROR("failed to %sable VDO: %d\n", -- ctrl == ENABLE ? "en" : "dis", ret); -- return ret; -- } -+ /* -+ * Apparently something about the firmware in the chip signals that -+ * HPD goes high by reporting GPIO9 as high (even though HPD isn't -+ * actually connected to GPIO9). -+ */ -+ ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status, -+ status & PS_GPIO9, 20 * 1000, 200 * 1000); - -- return 0; -+ if (ret < 0) -+ dev_warn(dev, "HPD didn't go high: %d\n", ret); -+ -+ return ret; - } - --static void ps8640_bridge_poweron(struct ps8640 *ps_bridge) -+static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux, -+ struct drm_dp_aux_msg *msg) - { -- struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL]; -- unsigned long timeout; -- int ret, status; -+ struct ps8640 *ps_bridge = aux_to_ps8640(aux); -+ struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL]; -+ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; -+ unsigned int len = msg->size; -+ unsigned int data; -+ unsigned int base; -+ int ret; -+ u8 request = msg->request & -+ ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); -+ u8 *buf = msg->buffer; -+ u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0]; -+ u8 i; -+ bool is_native_aux = false; - -- if (ps_bridge->powered) -- return; -+ if (len > DP_AUX_MAX_PAYLOAD_BYTES) -+ return -EINVAL; - -- ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), -- ps_bridge->supplies); -- if (ret < 0) { -- DRM_ERROR("cannot enable regulators %d\n", ret); -- return; -- } -+ if (msg->address & ~SWAUX_ADDR_MASK) -+ return -EINVAL; - -- gpiod_set_value(ps_bridge->gpio_powerdown, 0); -- gpiod_set_value(ps_bridge->gpio_reset, 1); -- usleep_range(2000, 2500); -- gpiod_set_value(ps_bridge->gpio_reset, 0); -+ switch (request) { -+ case DP_AUX_NATIVE_WRITE: -+ case DP_AUX_NATIVE_READ: -+ is_native_aux = true; -+ fallthrough; -+ case DP_AUX_I2C_WRITE: -+ case DP_AUX_I2C_READ: -+ break; -+ default: -+ return -EINVAL; -+ } - -- /* -- * Wait for the ps8640 embedded MCU to be ready -- * First wait 200ms and then check the MCU ready flag every 20ms -- */ -- msleep(200); -+ ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET); -+ if (ret) { -+ DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n", -+ ret); -+ return ret; -+ } - -- timeout = jiffies + msecs_to_jiffies(200) + 1; -+ /* Assume it's good */ -+ msg->reply = 0; - -- while (time_is_after_jiffies(timeout)) { -- status = i2c_smbus_read_byte_data(client, PAGE2_GPIO_H); -- if (status < 0) { -- DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", status); -- goto err_regulators_disable; -+ base = PAGE0_SWAUX_ADDR_7_0; -+ addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address; -+ addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8; -+ addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) | -+ (msg->request << 4); -+ addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD : -+ ((len - 1) & SWAUX_LENGTH_MASK); -+ -+ regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len, -+ ARRAY_SIZE(addr_len)); -+ -+ if (len && (request == DP_AUX_NATIVE_WRITE || -+ request == DP_AUX_I2C_WRITE)) { -+ /* Write to the internal FIFO buffer */ -+ for (i = 0; i < len; i++) { -+ ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]); -+ if (ret) { -+ DRM_DEV_ERROR(dev, -+ "failed to write WDATA: %d\n", -+ ret); -+ return ret; -+ } - } -- if ((status & PS_GPIO9) == PS_GPIO9) -- break; -- -- msleep(20); - } - -- msleep(50); -+ regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND); - -- /* -- * The Manufacturer Command Set (MCS) is a device dependent interface -- * intended for factory programming of the display module default -- * parameters. Once the display module is configured, the MCS shall be -- * disabled by the manufacturer. Once disabled, all MCS commands are -- * ignored by the display interface. -- */ -- status = i2c_smbus_read_byte_data(client, PAGE2_MCS_EN); -- if (status < 0) { -- DRM_ERROR("failed read PAGE2_MCS_EN: %d\n", status); -- goto err_regulators_disable; -+ /* Zero delay loop because i2c transactions are slow already */ -+ regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data, -+ !(data & SWAUX_SEND), 0, 50 * 1000); -+ -+ regmap_read(map, PAGE0_SWAUX_STATUS, &data); -+ if (ret) { -+ DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n", -+ ret); -+ return ret; - } - -- ret = i2c_smbus_write_byte_data(client, PAGE2_MCS_EN, -- status & ~MCS_EN); -- if (ret < 0) { -- DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret); -- goto err_regulators_disable; -+ switch (data & SWAUX_STATUS_MASK) { -+ /* Ignore the DEFER cases as they are already handled in hardware */ -+ case SWAUX_STATUS_NACK: -+ case SWAUX_STATUS_I2C_NACK: -+ /* -+ * The programming guide is not clear about whether a I2C NACK -+ * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So -+ * we handle both cases together. -+ */ -+ if (is_native_aux) -+ msg->reply |= DP_AUX_NATIVE_REPLY_NACK; -+ else -+ msg->reply |= DP_AUX_I2C_REPLY_NACK; -+ -+ fallthrough; -+ case SWAUX_STATUS_ACKM: -+ len = data & SWAUX_M_MASK; -+ break; -+ case SWAUX_STATUS_INVALID: -+ return -EOPNOTSUPP; -+ case SWAUX_STATUS_TIMEOUT: -+ return -ETIMEDOUT; - } - -- /* Switch access edp panel's edid through i2c */ -- ret = i2c_smbus_write_byte_data(client, PAGE2_I2C_BYPASS, -- I2C_BYPASS_EN); -- if (ret < 0) { -- DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret); -- goto err_regulators_disable; -+ if (len && (request == DP_AUX_NATIVE_READ || -+ request == DP_AUX_I2C_READ)) { -+ /* Read from the internal FIFO buffer */ -+ for (i = 0; i < len; i++) { -+ ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data); -+ if (ret) { -+ DRM_DEV_ERROR(dev, -+ "failed to read RDATA: %d\n", -+ ret); -+ return ret; -+ } -+ -+ buf[i] = data; -+ } - } - -- ps_bridge->powered = true; -+ return len; -+} -+ -+static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux, -+ struct drm_dp_aux_msg *msg) -+{ -+ struct ps8640 *ps_bridge = aux_to_ps8640(aux); -+ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; -+ int ret; - -- return; -+ pm_runtime_get_sync(dev); -+ ret = ps8640_ensure_hpd(ps_bridge); -+ if (!ret) -+ ret = ps8640_aux_transfer_msg(aux, msg); -+ pm_runtime_mark_last_busy(dev); -+ pm_runtime_put_autosuspend(dev); - --err_regulators_disable: -- regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), -- ps_bridge->supplies); -+ return ret; - } - --static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge) -+static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge, -+ const enum ps8640_vdo_control ctrl) - { -+ struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1]; -+ struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev; -+ u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl }; - int ret; - -- if (!ps_bridge->powered) -- return; -+ ret = regmap_bulk_write(map, PAGE3_SET_ADD, -+ vdo_ctrl_buf, sizeof(vdo_ctrl_buf)); -+ -+ if (ret < 0) -+ dev_err(dev, "failed to %sable VDO: %d\n", -+ ctrl == ENABLE ? "en" : "dis", ret); -+} -+ -+static int __maybe_unused ps8640_resume(struct device *dev) -+{ -+ struct ps8640 *ps_bridge = dev_get_drvdata(dev); -+ int ret; -+ -+ ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies), -+ ps_bridge->supplies); -+ if (ret < 0) { -+ dev_err(dev, "cannot enable regulators %d\n", ret); -+ return ret; -+ } -+ -+ gpiod_set_value(ps_bridge->gpio_powerdown, 0); -+ gpiod_set_value(ps_bridge->gpio_reset, 1); -+ usleep_range(2000, 2500); -+ gpiod_set_value(ps_bridge->gpio_reset, 0); -+ -+ /* -+ * Mystery 200 ms delay for the "MCU to be ready". It's unclear if -+ * this is truly necessary since the MCU will already signal that -+ * things are "good to go" by signaling HPD on "gpio 9". See -+ * ps8640_ensure_hpd(). For now we'll keep this mystery delay just in -+ * case. -+ */ -+ msleep(200); -+ -+ return 0; -+} -+ -+static int __maybe_unused ps8640_suspend(struct device *dev) -+{ -+ struct ps8640 *ps_bridge = dev_get_drvdata(dev); -+ int ret; - - gpiod_set_value(ps_bridge->gpio_reset, 1); - gpiod_set_value(ps_bridge->gpio_powerdown, 1); - ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies), - ps_bridge->supplies); - if (ret < 0) -- DRM_ERROR("cannot disable regulators %d\n", ret); -+ dev_err(dev, "cannot disable regulators %d\n", ret); - -- ps_bridge->powered = false; -+ return ret; - } - -+static const struct dev_pm_ops ps8640_pm_ops = { -+ SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL) -+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, -+ pm_runtime_force_resume) -+}; -+ - static void ps8640_pre_enable(struct drm_bridge *bridge) - { - struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); -+ struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL]; -+ struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; - int ret; - -- ps8640_bridge_poweron(ps_bridge); -+ pm_runtime_get_sync(dev); -+ ps8640_ensure_hpd(ps_bridge); - -- ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE); -+ /* -+ * The Manufacturer Command Set (MCS) is a device dependent interface -+ * intended for factory programming of the display module default -+ * parameters. Once the display module is configured, the MCS shall be -+ * disabled by the manufacturer. Once disabled, all MCS commands are -+ * ignored by the display interface. -+ */ -+ -+ ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0); -+ if (ret < 0) -+ dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); -+ -+ /* Switch access edp panel's edid through i2c */ -+ ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN); - if (ret < 0) -- ps8640_bridge_poweroff(ps_bridge); -+ dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret); -+ -+ ps8640_bridge_vdo_control(ps_bridge, ENABLE); -+ -+ ps_bridge->pre_enabled = true; - } - - static void ps8640_post_disable(struct drm_bridge *bridge) - { - struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); - -+ ps_bridge->pre_enabled = false; -+ - ps8640_bridge_vdo_control(ps_bridge, DISABLE); -- ps8640_bridge_poweroff(ps_bridge); -+ pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev); - } - - static int ps8640_bridge_attach(struct drm_bridge *bridge, -@@ -254,25 +484,40 @@ - dsi->mode_flags = MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE; - dsi->format = MIPI_DSI_FMT_RGB888; -- dsi->lanes = DP_NUM_LANES; -+ dsi->lanes = NUM_MIPI_LANES; - ret = mipi_dsi_attach(dsi); -- if (ret) -+ if (ret) { -+ dev_err(dev, "failed to attach dsi device: %d\n", ret); - goto err_dsi_attach; -+ } -+ -+ ret = drm_dp_aux_register(&ps_bridge->aux); -+ if (ret) { -+ dev_err(dev, "failed to register DP AUX channel: %d\n", ret); -+ goto err_aux_register; -+ } - - /* Attach the panel-bridge to the dsi bridge */ - return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge, - &ps_bridge->bridge, flags); - -+err_aux_register: -+ mipi_dsi_detach(dsi); - err_dsi_attach: - mipi_dsi_device_unregister(dsi); - return ret; - } - -+static void ps8640_bridge_detach(struct drm_bridge *bridge) -+{ -+ drm_dp_aux_unregister(&bridge_to_ps8640(bridge)->aux); -+} -+ - static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, - struct drm_connector *connector) - { - struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); -- bool poweroff = !ps_bridge->powered; -+ bool poweroff = !ps_bridge->pre_enabled; - struct edid *edid; - - /* -@@ -302,8 +547,15 @@ - return edid; - } - -+static void ps8640_runtime_disable(void *data) -+{ -+ pm_runtime_dont_use_autosuspend(data); -+ pm_runtime_disable(data); -+} -+ - static const struct drm_bridge_funcs ps8640_bridge_funcs = { - .attach = ps8640_bridge_attach, -+ .detach = ps8640_bridge_detach, - .get_edid = ps8640_bridge_get_edid, - .post_disable = ps8640_post_disable, - .pre_enable = ps8640_pre_enable, -@@ -322,17 +574,6 @@ - if (!ps_bridge) - return -ENOMEM; - -- /* port@1 is ps8640 output port */ -- ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); -- if (ret < 0) -- return ret; -- if (!panel) -- return -ENODEV; -- -- ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel); -- if (IS_ERR(ps_bridge->panel_bridge)) -- return PTR_ERR(ps_bridge->panel_bridge); -- - ps_bridge->supplies[0].supply = "vdd33"; - ps_bridge->supplies[1].supply = "vdd12"; - ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies), -@@ -355,24 +596,71 @@ - - ps_bridge->bridge.funcs = &ps8640_bridge_funcs; - ps_bridge->bridge.of_node = dev->of_node; -- ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID; - ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP; - -+ /* -+ * In the device tree, if panel is listed under aux-bus of the bridge -+ * node, panel driver should be able to retrieve EDID by itself using -+ * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here. -+ */ -+ if (!ps8640_of_panel_on_aux_bus(&client->dev)) -+ ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID; -+ - ps_bridge->page[PAGE0_DP_CNTL] = client; - -+ ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config); -+ if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL])) -+ return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]); -+ - for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) { - ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev, - client->adapter, - client->addr + i); -- if (IS_ERR(ps_bridge->page[i])) { -- dev_err(dev, "failed i2c dummy device, address %02x\n", -- client->addr + i); -+ if (IS_ERR(ps_bridge->page[i])) - return PTR_ERR(ps_bridge->page[i]); -- } -+ -+ ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i], -+ ps8640_regmap_config + i); -+ if (IS_ERR(ps_bridge->regmap[i])) -+ return PTR_ERR(ps_bridge->regmap[i]); - } - - i2c_set_clientdata(client, ps_bridge); - -+ ps_bridge->aux.name = "parade-ps8640-aux"; -+ ps_bridge->aux.dev = dev; -+ ps_bridge->aux.transfer = ps8640_aux_transfer; -+ drm_dp_aux_init(&ps_bridge->aux); -+ -+ pm_runtime_enable(dev); -+ /* -+ * Powering on ps8640 takes ~300ms. To avoid wasting time on power -+ * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure -+ * the bridge wouldn't suspend in between each _aux_transfer_msg() call -+ * during EDID read (~20ms in my experiment) and in between the last -+ * _aux_transfer_msg() call during EDID read and the _pre_enable() call -+ * (~100ms in my experiment). -+ */ -+ pm_runtime_set_autosuspend_delay(dev, 1000); -+ pm_runtime_use_autosuspend(dev); -+ pm_suspend_ignore_children(dev, true); -+ ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev); -+ if (ret) -+ return ret; -+ -+ devm_of_dp_aux_populate_ep_devices(&ps_bridge->aux); -+ -+ /* port@1 is ps8640 output port */ -+ ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL); -+ if (ret < 0) -+ return ret; -+ if (!panel) -+ return -ENODEV; -+ -+ ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel); -+ if (IS_ERR(ps_bridge->panel_bridge)) -+ return PTR_ERR(ps_bridge->panel_bridge); -+ - drm_bridge_add(&ps_bridge->bridge); - - return 0; -@@ -399,6 +687,7 @@ - .driver = { - .name = "ps8640", - .of_match_table = ps8640_match, -+ .pm = &ps8640_pm_ops, - }, - }; - module_i2c_driver(ps8640_driver); diff -ruN a/drivers/gpu/drm/drm_auth.c b/drivers/gpu/drm/drm_auth.c --- a/drivers/gpu/drm/drm_auth.c 2021-12-08 09:04:57.000000000 +0100 +++ b/drivers/gpu/drm/drm_auth.c 2021-12-23 08:35:26.000000000 +0100 diff --git a/kernel-patches/chromebook-5.4/chromeos/lsm_shmem.patch b/kernel-patches/chromebook-5.4/chromeos/lsm_shmem.patch index cad40a097..2967cf81b 100644 --- a/kernel-patches/chromebook-5.4/chromeos/lsm_shmem.patch +++ b/kernel-patches/chromebook-5.4/chromeos/lsm_shmem.patch @@ -1,11 +1,10 @@ --- ./security/chromiumos/lsm.c 2022-09-28 07:26:42.949182359 +0200 +++ ./security/chromiumos/lsm.c 2022-09-28 07:29:28.984937913 +0200 -@@ -217,7 +217,7 @@ +@@ -217,6 +217,7 @@ + static int chromiumos_bprm_creds_for_exec(struct linux_binprm *bprm) + { struct file *file = bprm->file; ++ return 0; - if (shmem_file(file)) -- return -EACCES; -+ return 0; - - return 0; - } + if (shmem_file(file)) { + char *cmdline = printable_cmdline(current); diff --git a/kernel-patches/macbook/chromeos/lsm_shmem.patch b/kernel-patches/macbook/chromeos/lsm_shmem.patch index cad40a097..2967cf81b 100644 --- a/kernel-patches/macbook/chromeos/lsm_shmem.patch +++ b/kernel-patches/macbook/chromeos/lsm_shmem.patch @@ -1,11 +1,10 @@ --- ./security/chromiumos/lsm.c 2022-09-28 07:26:42.949182359 +0200 +++ ./security/chromiumos/lsm.c 2022-09-28 07:29:28.984937913 +0200 -@@ -217,7 +217,7 @@ +@@ -217,6 +217,7 @@ + static int chromiumos_bprm_creds_for_exec(struct linux_binprm *bprm) + { struct file *file = bprm->file; ++ return 0; - if (shmem_file(file)) -- return -EACCES; -+ return 0; - - return 0; - } + if (shmem_file(file)) { + char *cmdline = printable_cmdline(current); diff --git a/prepare_kernels.sh b/prepare_kernels.sh index 54994d0e8..5878fb35d 100755 --- a/prepare_kernels.sh +++ b/prepare_kernels.sh @@ -124,6 +124,6 @@ done rm -rf ./kernels mkdir ./kernels -chromeos_version="R108" +chromeos_version="R109" download_and_patch_kernels