diff --git a/common/driver/data_dev_top.c b/common/driver/data_dev_top.c
index ac4e9d0..7218fca 100755
--- a/common/driver/data_dev_top.c
+++ b/common/driver/data_dev_top.c
@@ -383,7 +383,7 @@ int32_t DataDev_Command(struct DmaDevice *dev, uint32_t cmd, uint64_t arg) {
       case GPU_Add_Nvidia_Memory:
       case GPU_Rem_Nvidia_Memory:
       case GPU_Set_Write_Enable:
-         return Gpu_Command(dev, cmd, arg);
+         return dev->gpuEn ? Gpu_Command(dev, cmd, arg) : -1;
 #endif
 
       case AVER_Get:
@@ -423,8 +423,10 @@ void DataDev_SeqShow(struct seq_file *s, struct DmaDevice *dev) {
    AxisG2_SeqShow(s, dev);
 
 #ifdef DATA_GPU
-   // Display DataGPU-specific state information
-   Gpu_Show(s, dev);
+   if (dev->gpuEn) {
+      // Display DataGPU-specific state information
+      Gpu_Show(s, dev);
+   }
 #endif
 }
 
diff --git a/common/driver/dma_common.h b/common/driver/dma_common.h
index 1273825..3ce9961 100755
--- a/common/driver/dma_common.h
+++ b/common/driver/dma_common.h
@@ -121,6 +121,9 @@ struct DmaDevice {
    // Debug flag
    uint8_t debug;
 
+   // GPU-capable flag
+   uint8_t gpuEn;
+
    // IRQ
    uint32_t irq;
 
diff --git a/common/driver/gpu_async.c b/common/driver/gpu_async.c
index ef50074..7dfb46c 100755
--- a/common/driver/gpu_async.c
+++ b/common/driver/gpu_async.c
@@ -38,6 +38,13 @@
 void Gpu_Init(struct DmaDevice *dev, uint32_t offset) {
    struct GpuData *gpuData;
 
+   uint8_t* gpuBase = dev->base + offset;
+   dev->gpuEn = !!readGpuAsyncReg(gpuBase, &GpuAsyncReg_Version);
+
+   /* GPU not enabled, avoid allocating GPU data */
+   if (!dev->gpuEn)
+      return;
+
    /* Allocate memory for GPU utility data */
    gpuData = (struct GpuData *)kzalloc(sizeof(struct GpuData), GFP_KERNEL);
    if (!gpuData)
diff --git a/include/GpuAsyncRegs.h b/include/GpuAsyncRegs.h
index c16df1c..4817295 100755
--- a/include/GpuAsyncRegs.h
+++ b/include/GpuAsyncRegs.h
@@ -82,6 +82,8 @@ GPU_ASYNC_DEF_REG(DynamicRouteDests0, 0x2C, 8,  0xFF00);
 GPU_ASYNC_DEF_REG(DynamicRouteMasks1, 0x2C, 16, 0xFF0000);
 GPU_ASYNC_DEF_REG(DynamicRouteDests1, 0x2C, 24, 0xFF000000);
 
+GPU_ASYNC_DEF_REG(Version, 0x30, 0, 0x1);
+
 // The following register defintiions are firmware specific. GpuAsyncCore can have up to 16 buffers, but defaults to 4.
 // You must check the MaxBuffers register for the true value