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libxdma.c
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/*******************************************************************************
*
* Xilinx XDMA IP Core Linux Driver
* Copyright(c) 2015 - 2017 Xilinx, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*
* The full GNU General Public License is included in this distribution in
* the file called "LICENSE".
*
* Karen Xie <[email protected]>
*
******************************************************************************/
#define pr_fmt(fmt) KBUILD_MODNAME ":%s: " fmt, __func__
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include "libxdma.h"
#include "libxdma_api.h"
/* SECTION: Module licensing */
#ifdef __LIBXDMA_MOD__
#include "version.h"
#define DRV_MODULE_NAME "libxdma"
#define DRV_MODULE_DESC "Xilinx XDMA Base Driver"
#define DRV_MODULE_RELDATE "Feb. 2017"
static char version[] =
DRV_MODULE_DESC " " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
MODULE_AUTHOR("Xilinx, Inc.");
MODULE_DESCRIPTION(DRV_MODULE_DESC);
MODULE_VERSION(DRV_MODULE_VERSION);
MODULE_LICENSE("GPL v2");
#endif
/* Module Parameters */
static unsigned int poll_mode;
module_param(poll_mode, uint, 0644);
MODULE_PARM_DESC(poll_mode, "Set 1 for hw polling, default is 0 (interrupts)");
static unsigned int interrupt_mode;
#ifdef INTERNAL_TESTING
module_param(interrupt_mode, uint, 0644);
MODULE_PARM_DESC(interrupt_mode, "0 - MSI-x , 1 - MSI, 2 - Legacy");
#endif
static unsigned int enable_credit_mp;
#ifdef INTERNAL_TESTING
module_param(enable_credit_mp, uint, 0644);
MODULE_PARM_DESC(enable_credit_mp, "Set 1 to enable creidt feature, default is 0 (no credit control)");
#endif
unsigned int desc_blen_max = XDMA_DESC_BLEN_MAX;
module_param(desc_blen_max, uint, 0644);
MODULE_PARM_DESC(desc_blen_max, "per descriptor max. buffer length, default is (1 << 28) - 1");
/*
* xdma device management
* maintains a list of the xdma devices
*/
static LIST_HEAD(xdev_list);
static DEFINE_MUTEX(xdev_mutex);
static LIST_HEAD(xdev_rcu_list);
static DEFINE_SPINLOCK(xdev_rcu_lock);
#ifndef list_last_entry
#define list_last_entry(ptr, type, member) \
list_entry((ptr)->prev, type, member)
#endif
static inline void xdev_list_add(struct xdma_dev *xdev)
{
mutex_lock(&xdev_mutex);
if (list_empty(&xdev_list))
xdev->idx = 0;
else {
struct xdma_dev *last;
last = list_last_entry(&xdev_list, struct xdma_dev, list_head);
xdev->idx = last->idx + 1;
}
list_add_tail(&xdev->list_head, &xdev_list);
mutex_unlock(&xdev_mutex);
dbg_init("dev %s, xdev 0x%p, xdma idx %d.\n",
dev_name(&xdev->pdev->dev), xdev, xdev->idx);
spin_lock(&xdev_rcu_lock);
list_add_tail_rcu(&xdev->rcu_node, &xdev_rcu_list);
spin_unlock(&xdev_rcu_lock);
}
#undef list_last_entry
static inline void xdev_list_remove(struct xdma_dev *xdev)
{
mutex_lock(&xdev_mutex);
list_del(&xdev->list_head);
mutex_unlock(&xdev_mutex);
spin_lock(&xdev_rcu_lock);
list_del_rcu(&xdev->rcu_node);
spin_unlock(&xdev_rcu_lock);
synchronize_rcu();
}
struct xdma_dev *xdev_find_by_pdev(struct pci_dev *pdev)
{
struct xdma_dev *xdev, *tmp;
mutex_lock(&xdev_mutex);
list_for_each_entry_safe(xdev, tmp, &xdev_list, list_head) {
if (xdev->pdev == pdev) {
mutex_unlock(&xdev_mutex);
return xdev;
}
}
mutex_unlock(&xdev_mutex);
return NULL;
}
EXPORT_SYMBOL_GPL(xdev_find_by_pdev);
static inline int debug_check_dev_hndl(const char *fname, struct pci_dev *pdev,
void *hndl)
{
struct xdma_dev *xdev;
if (!pdev)
return -EINVAL;
xdev = xdev_find_by_pdev(pdev);
if (!xdev) {
pr_info("%s pdev 0x%p, hndl 0x%p, NO match found!\n",
fname, pdev, hndl);
return -EINVAL;
}
if (xdev != hndl) {
pr_err("%s pdev 0x%p, hndl 0x%p != 0x%p!\n",
fname, pdev, hndl, xdev);
return -EINVAL;
}
return 0;
}
#ifdef __LIBXDMA_DEBUG__
/* SECTION: Function definitions */
inline void __write_register(const char *fn, u32 value, void *iomem, unsigned long off)
{
pr_err("%s: w reg 0x%lx(0x%p), 0x%x.\n", fn, off, iomem, value);
iowrite32(value, iomem);
}
#define write_register(v,mem,off) __write_register(__func__, v, mem, off)
#else
#define write_register(v,mem,off) iowrite32(v, mem)
#endif
inline u32 read_register(void *iomem)
{
return ioread32(iomem);
}
static inline u32 build_u32(u32 hi, u32 lo)
{
return ((hi & 0xFFFFUL) << 16) | (lo & 0xFFFFUL);
}
static inline u64 build_u64(u64 hi, u64 lo)
{
return ((hi & 0xFFFFFFFULL) << 32) | (lo & 0xFFFFFFFFULL);
}
static void check_nonzero_interrupt_status(struct xdma_dev *xdev)
{
struct interrupt_regs *reg = (struct interrupt_regs *)
(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);
u32 w;
w = read_register(®->user_int_enable);
if (w)
pr_info("%s xdma%d user_int_enable = 0x%08x\n",
dev_name(&xdev->pdev->dev), xdev->idx, w);
w = read_register(®->channel_int_enable);
if (w)
pr_info("%s xdma%d channel_int_enable = 0x%08x\n",
dev_name(&xdev->pdev->dev), xdev->idx, w);
w = read_register(®->user_int_request);
if (w)
pr_info("%s xdma%d user_int_request = 0x%08x\n",
dev_name(&xdev->pdev->dev), xdev->idx, w);
w = read_register(®->channel_int_request);
if (w)
pr_info("%s xdma%d channel_int_request = 0x%08x\n",
dev_name(&xdev->pdev->dev), xdev->idx, w);
w = read_register(®->user_int_pending);
if (w)
pr_info("%s xdma%d user_int_pending = 0x%08x\n",
dev_name(&xdev->pdev->dev), xdev->idx, w);
w = read_register(®->channel_int_pending);
if (w)
pr_info("%s xdma%d channel_int_pending = 0x%08x\n",
dev_name(&xdev->pdev->dev), xdev->idx, w);
}
/* channel_interrupts_enable -- Enable interrupts we are interested in */
static void channel_interrupts_enable(struct xdma_dev *xdev, u32 mask)
{
struct interrupt_regs *reg = (struct interrupt_regs *)
(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);
write_register(mask, ®->channel_int_enable_w1s, XDMA_OFS_INT_CTRL);
}
/* channel_interrupts_disable -- Disable interrupts we not interested in */
static void channel_interrupts_disable(struct xdma_dev *xdev, u32 mask)
{
struct interrupt_regs *reg = (struct interrupt_regs *)
(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);
write_register(mask, ®->channel_int_enable_w1c, XDMA_OFS_INT_CTRL);
}
/* user_interrupts_enable -- Enable interrupts we are interested in */
static void user_interrupts_enable(struct xdma_dev *xdev, u32 mask)
{
struct interrupt_regs *reg = (struct interrupt_regs *)
(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);
write_register(mask, ®->user_int_enable_w1s, XDMA_OFS_INT_CTRL);
}
/* user_interrupts_disable -- Disable interrupts we not interested in */
static void user_interrupts_disable(struct xdma_dev *xdev, u32 mask)
{
struct interrupt_regs *reg = (struct interrupt_regs *)
(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);
write_register(mask, ®->user_int_enable_w1c, XDMA_OFS_INT_CTRL);
}
/* read_interrupts -- Print the interrupt controller status */
static u32 read_interrupts(struct xdma_dev *xdev)
{
struct interrupt_regs *reg = (struct interrupt_regs *)
(xdev->bar[xdev->config_bar_idx] + XDMA_OFS_INT_CTRL);
u32 lo;
u32 hi;
/* extra debugging; inspect complete engine set of registers */
hi = read_register(®->user_int_request);
dbg_io("ioread32(0x%p) returned 0x%08x (user_int_request).\n",
®->user_int_request, hi);
lo = read_register(®->channel_int_request);
dbg_io("ioread32(0x%p) returned 0x%08x (channel_int_request)\n",
®->channel_int_request, lo);
/* return interrupts: user in upper 16-bits, channel in lower 16-bits */
return build_u32(hi, lo);
}
void enable_perf(struct xdma_engine *engine)
{
u32 w;
w = XDMA_PERF_CLEAR;
write_register(w, &engine->regs->perf_ctrl,
(unsigned long)(&engine->regs->perf_ctrl) -
(unsigned long)(&engine->regs));
read_register(&engine->regs->identifier);
w = XDMA_PERF_AUTO | XDMA_PERF_RUN;
write_register(w, &engine->regs->perf_ctrl,
(unsigned long)(&engine->regs->perf_ctrl) -
(unsigned long)(&engine->regs));
read_register(&engine->regs->identifier);
dbg_perf("IOCTL_XDMA_PERF_START\n");
}
EXPORT_SYMBOL_GPL(enable_perf);
#ifdef INTERNAL_TESTING
void get_perf_stats(struct xdma_engine *engine)
{
u32 hi;
u32 lo;
BUG_ON(!engine);
if (!engine->xdma_perf) {
pr_info("%s perf struct not set up.\n", engine->name);
return;
}
hi = 0;
lo = read_register(&engine->regs->completed_desc_count);
engine->xdma_perf->iterations = build_u64(hi, lo);
hi = read_register(&engine->regs->perf_cyc_hi);
lo = read_register(&engine->regs->perf_cyc_lo);
engine->xdma_perf->clock_cycle_count = build_u64(hi, lo);
hi = read_register(&engine->regs->perf_dat_hi);
lo = read_register(&engine->regs->perf_dat_lo);
engine->xdma_perf->data_cycle_count = build_u64(hi, lo);
hi = read_register(&engine->regs->perf_pnd_hi);
lo = read_register(&engine->regs->perf_pnd_lo);
engine->xdma_perf->pending_count = build_u64(hi, lo);
}
EXPORT_SYMBOL_GPL(get_perf_stats);
#endif
static void engine_reg_dump(struct xdma_engine *engine)
{
u32 w;
BUG_ON(!engine);
w = read_register(&engine->regs->identifier);
pr_info("%s: ioread32(0x%p) = 0x%08x (id).\n",
engine->name, &engine->regs->identifier, w);
w &= BLOCK_ID_MASK;
if (w != BLOCK_ID_HEAD) {
pr_info("%s: engine id missing, 0x%08x exp. & 0x%x = 0x%x\n",
engine->name, w, BLOCK_ID_MASK, BLOCK_ID_HEAD);
return;
}
/* extra debugging; inspect complete engine set of registers */
w = read_register(&engine->regs->status);
pr_info("%s: ioread32(0x%p) = 0x%08x (status).\n",
engine->name, &engine->regs->status, w);
w = read_register(&engine->regs->control);
pr_info("%s: ioread32(0x%p) = 0x%08x (control)\n",
engine->name, &engine->regs->control, w);
w = read_register(&engine->sgdma_regs->first_desc_lo);
pr_info("%s: ioread32(0x%p) = 0x%08x (first_desc_lo)\n",
engine->name, &engine->sgdma_regs->first_desc_lo, w);
w = read_register(&engine->sgdma_regs->first_desc_hi);
pr_info("%s: ioread32(0x%p) = 0x%08x (first_desc_hi)\n",
engine->name, &engine->sgdma_regs->first_desc_hi, w);
w = read_register(&engine->sgdma_regs->first_desc_adjacent);
pr_info("%s: ioread32(0x%p) = 0x%08x (first_desc_adjacent).\n",
engine->name, &engine->sgdma_regs->first_desc_adjacent, w);
w = read_register(&engine->regs->completed_desc_count);
pr_info("%s: ioread32(0x%p) = 0x%08x (completed_desc_count).\n",
engine->name, &engine->regs->completed_desc_count, w);
w = read_register(&engine->regs->interrupt_enable_mask);
pr_info("%s: ioread32(0x%p) = 0x%08x (interrupt_enable_mask)\n",
engine->name, &engine->regs->interrupt_enable_mask, w);
}
/**
* engine_status_read() - read status of SG DMA engine (optionally reset)
*
* Stores status in engine->status.
*
* @return -1 on failure, status register otherwise
*/
static void engine_status_dump(struct xdma_engine *engine)
{
u32 v = engine->status;
char buffer[256];
char *buf = buffer;
int len = 0;
len = sprintf(buf, "SG engine %s status: 0x%08x: ", engine->name, v);
if ((v & XDMA_STAT_BUSY))
len += sprintf(buf + len, "BUSY,");
if ((v & XDMA_STAT_DESC_STOPPED))
len += sprintf(buf + len, "DESC_STOPPED,");
if ((v & XDMA_STAT_DESC_COMPLETED))
len += sprintf(buf + len, "DESC_COMPL,");
/* common H2C & C2H */
if ((v & XDMA_STAT_COMMON_ERR_MASK)) {
if ((v & XDMA_STAT_ALIGN_MISMATCH))
len += sprintf(buf + len, "ALIGN_MISMATCH ");
if ((v & XDMA_STAT_MAGIC_STOPPED))
len += sprintf(buf + len, "MAGIC_STOPPED ");
if ((v & XDMA_STAT_INVALID_LEN))
len += sprintf(buf + len, "INVLIAD_LEN ");
if ((v & XDMA_STAT_IDLE_STOPPED))
len += sprintf(buf + len, "IDLE_STOPPED ");
buf[len - 1] = ',';
}
if ((engine->dir == DMA_TO_DEVICE)) {
/* H2C only */
if ((v & XDMA_STAT_H2C_R_ERR_MASK)) {
len += sprintf(buf + len, "R:");
if ((v & XDMA_STAT_H2C_R_UNSUPP_REQ))
len += sprintf(buf + len, "UNSUPP_REQ ");
if ((v & XDMA_STAT_H2C_R_COMPL_ABORT))
len += sprintf(buf + len, "COMPL_ABORT ");
if ((v & XDMA_STAT_H2C_R_PARITY_ERR))
len += sprintf(buf + len, "PARITY ");
if ((v & XDMA_STAT_H2C_R_HEADER_EP))
len += sprintf(buf + len, "HEADER_EP ");
if ((v & XDMA_STAT_H2C_R_UNEXP_COMPL))
len += sprintf(buf + len, "UNEXP_COMPL ");
buf[len - 1] = ',';
}
if ((v & XDMA_STAT_H2C_W_ERR_MASK)) {
len += sprintf(buf + len, "W:");
if ((v & XDMA_STAT_H2C_W_DECODE_ERR))
len += sprintf(buf + len, "DECODE_ERR ");
if ((v & XDMA_STAT_H2C_W_SLAVE_ERR))
len += sprintf(buf + len, "SLAVE_ERR ");
buf[len - 1] = ',';
}
} else {
/* C2H only */
if ((v & XDMA_STAT_C2H_R_ERR_MASK)) {
len += sprintf(buf + len, "R:");
if ((v & XDMA_STAT_C2H_R_DECODE_ERR))
len += sprintf(buf + len, "DECODE_ERR ");
if ((v & XDMA_STAT_C2H_R_SLAVE_ERR))
len += sprintf(buf + len, "SLAVE_ERR ");
buf[len - 1] = ',';
}
}
/* common H2C & C2H */
if ((v & XDMA_STAT_DESC_ERR_MASK)) {
len += sprintf(buf + len, "DESC_ERR:");
if ((v & XDMA_STAT_DESC_UNSUPP_REQ))
len += sprintf(buf + len, "UNSUPP_REQ ");
if ((v & XDMA_STAT_DESC_COMPL_ABORT))
len += sprintf(buf + len, "COMPL_ABORT ");
if ((v & XDMA_STAT_DESC_PARITY_ERR))
len += sprintf(buf + len, "PARITY ");
if ((v & XDMA_STAT_DESC_HEADER_EP))
len += sprintf(buf + len, "HEADER_EP ");
if ((v & XDMA_STAT_DESC_UNEXP_COMPL))
len += sprintf(buf + len, "UNEXP_COMPL ");
buf[len - 1] = ',';
}
buf[len - 1] = '\0';
pr_info("%s\n", buffer);
}
static u32 engine_status_read(struct xdma_engine *engine, bool clear, bool dump)
{
u32 value;
BUG_ON(!engine);
if (dump)
engine_reg_dump(engine);
/* read status register */
if (clear)
value = engine->status =
read_register(&engine->regs->status_rc);
else
value = engine->status = read_register(&engine->regs->status);
if (dump)
engine_status_dump(engine);
return value;
}
/**
* xdma_engine_stop() - stop an SG DMA engine
*
*/
static void xdma_engine_stop(struct xdma_engine *engine)
{
u32 w;
BUG_ON(!engine);
dbg_tfr("xdma_engine_stop(engine=%p)\n", engine);
w = 0;
w |= (u32)XDMA_CTRL_IE_DESC_ALIGN_MISMATCH;
w |= (u32)XDMA_CTRL_IE_MAGIC_STOPPED;
w |= (u32)XDMA_CTRL_IE_READ_ERROR;
w |= (u32)XDMA_CTRL_IE_DESC_ERROR;
if (poll_mode) {
w |= (u32) XDMA_CTRL_POLL_MODE_WB;
} else {
w |= (u32)XDMA_CTRL_IE_DESC_STOPPED;
w |= (u32)XDMA_CTRL_IE_DESC_COMPLETED;
/* Disable IDLE STOPPED for MM */
if ((engine->streaming && (engine->dir == DMA_FROM_DEVICE)) ||
(engine->xdma_perf))
w |= (u32)XDMA_CTRL_IE_IDLE_STOPPED;
}
dbg_tfr("Stopping SG DMA %s engine; writing 0x%08x to 0x%p.\n",
engine->name, w, (u32 *)&engine->regs->control);
write_register(w, &engine->regs->control,
(unsigned long)(&engine->regs->control) -
(unsigned long)(&engine->regs));
/* dummy read of status register to flush all previous writes */
dbg_tfr("xdma_engine_stop(%s) done\n", engine->name);
}
static void engine_start_mode_config(struct xdma_engine *engine)
{
u32 w;
BUG_ON(!engine);
/* If a perf test is running, enable the engine interrupts */
if (engine->xdma_perf) {
w = XDMA_CTRL_IE_DESC_STOPPED;
w |= XDMA_CTRL_IE_DESC_COMPLETED;
w |= XDMA_CTRL_IE_DESC_ALIGN_MISMATCH;
w |= XDMA_CTRL_IE_MAGIC_STOPPED;
w |= XDMA_CTRL_IE_IDLE_STOPPED;
w |= XDMA_CTRL_IE_READ_ERROR;
w |= XDMA_CTRL_IE_DESC_ERROR;
write_register(w, &engine->regs->interrupt_enable_mask,
(unsigned long)(&engine->regs->interrupt_enable_mask) -
(unsigned long)(&engine->regs));
}
/* write control register of SG DMA engine */
w = (u32)XDMA_CTRL_RUN_STOP;
w |= (u32)XDMA_CTRL_IE_READ_ERROR;
w |= (u32)XDMA_CTRL_IE_DESC_ERROR;
w |= (u32)XDMA_CTRL_IE_DESC_ALIGN_MISMATCH;
w |= (u32)XDMA_CTRL_IE_MAGIC_STOPPED;
if (poll_mode) {
w |= (u32)XDMA_CTRL_POLL_MODE_WB;
} else {
w |= (u32)XDMA_CTRL_IE_DESC_STOPPED;
w |= (u32)XDMA_CTRL_IE_DESC_COMPLETED;
if ((engine->streaming && (engine->dir == DMA_FROM_DEVICE)) ||
(engine->xdma_perf))
w |= (u32)XDMA_CTRL_IE_IDLE_STOPPED;
/* set non-incremental addressing mode */
if (engine->non_incr_addr)
w |= (u32)XDMA_CTRL_NON_INCR_ADDR;
}
dbg_tfr("iowrite32(0x%08x to 0x%p) (control)\n", w,
(void *)&engine->regs->control);
/* start the engine */
write_register(w, &engine->regs->control,
(unsigned long)(&engine->regs->control) -
(unsigned long)(&engine->regs));
/* dummy read of status register to flush all previous writes */
w = read_register(&engine->regs->status);
dbg_tfr("ioread32(0x%p) = 0x%08x (dummy read flushes writes).\n",
&engine->regs->status, w);
}
/**
* engine_start() - start an idle engine with its first transfer on queue
*
* The engine will run and process all transfers that are queued using
* transfer_queue() and thus have their descriptor lists chained.
*
* During the run, new transfers will be processed if transfer_queue() has
* chained the descriptors before the hardware fetches the last descriptor.
* A transfer that was chained too late will invoke a new run of the engine
* initiated from the engine_service() routine.
*
* The engine must be idle and at least one transfer must be queued.
* This function does not take locks; the engine spinlock must already be
* taken.
*
*/
static struct xdma_transfer *engine_start(struct xdma_engine *engine)
{
struct xdma_transfer *transfer;
u32 w;
int extra_adj = 0;
/* engine must be idle */
BUG_ON(engine->running);
/* engine transfer queue must not be empty */
BUG_ON(list_empty(&engine->transfer_list));
/* inspect first transfer queued on the engine */
transfer = list_entry(engine->transfer_list.next, struct xdma_transfer,
entry);
BUG_ON(!transfer);
/* engine is no longer shutdown */
engine->shutdown = ENGINE_SHUTDOWN_NONE;
dbg_tfr("engine_start(%s): transfer=0x%p.\n", engine->name, transfer);
/* initialize number of descriptors of dequeued transfers */
engine->desc_dequeued = 0;
/* write lower 32-bit of bus address of transfer first descriptor */
w = cpu_to_le32(PCI_DMA_L(transfer->desc_bus));
dbg_tfr("iowrite32(0x%08x to 0x%p) (first_desc_lo)\n", w,
(void *)&engine->sgdma_regs->first_desc_lo);
write_register(w, &engine->sgdma_regs->first_desc_lo,
(unsigned long)(&engine->sgdma_regs->first_desc_lo) -
(unsigned long)(&engine->sgdma_regs));
/* write upper 32-bit of bus address of transfer first descriptor */
w = cpu_to_le32(PCI_DMA_H(transfer->desc_bus));
dbg_tfr("iowrite32(0x%08x to 0x%p) (first_desc_hi)\n", w,
(void *)&engine->sgdma_regs->first_desc_hi);
write_register(w, &engine->sgdma_regs->first_desc_hi,
(unsigned long)(&engine->sgdma_regs->first_desc_hi) -
(unsigned long)(&engine->sgdma_regs));
if (transfer->desc_adjacent > 0) {
extra_adj = transfer->desc_adjacent - 1;
if (extra_adj > MAX_EXTRA_ADJ)
extra_adj = MAX_EXTRA_ADJ;
}
dbg_tfr("iowrite32(0x%08x to 0x%p) (first_desc_adjacent)\n",
extra_adj, (void *)&engine->sgdma_regs->first_desc_adjacent);
write_register(extra_adj, &engine->sgdma_regs->first_desc_adjacent,
(unsigned long)(&engine->sgdma_regs->first_desc_adjacent) -
(unsigned long)(&engine->sgdma_regs));
dbg_tfr("ioread32(0x%p) (dummy read flushes writes).\n",
&engine->regs->status);
mmiowb();
engine_start_mode_config(engine);
engine_status_read(engine, 0, 0);
dbg_tfr("%s engine 0x%p now running\n", engine->name, engine);
/* remember the engine is running */
engine->running = 1;
return transfer;
}
/**
* engine_service() - service an SG DMA engine
*
* must be called with engine->lock already acquired
*
* @engine pointer to struct xdma_engine
*
*/
static void engine_service_shutdown(struct xdma_engine *engine)
{
/* if the engine stopped with RUN still asserted, de-assert RUN now */
dbg_tfr("engine just went idle, resetting RUN_STOP.\n");
xdma_engine_stop(engine);
engine->running = 0;
/* awake task on engine's shutdown wait queue */
wake_up_interruptible(&engine->shutdown_wq);
}
struct xdma_transfer *engine_transfer_completion(struct xdma_engine *engine,
struct xdma_transfer *transfer)
{
BUG_ON(!engine);
if (unlikely(!transfer)) {
pr_info("%s: xfer empty.\n", engine->name);
return NULL;
}
/* synchronous I/O? */
/* awake task on transfer's wait queue */
wake_up_interruptible(&transfer->wq);
return transfer;
}
struct xdma_transfer *engine_service_transfer_list(struct xdma_engine *engine,
struct xdma_transfer *transfer, u32 *pdesc_completed)
{
BUG_ON(!engine);
BUG_ON(!pdesc_completed);
if (unlikely(!transfer)) {
pr_info("%s xfer empty, pdesc completed %u.\n",
engine->name, *pdesc_completed);
return NULL;
}
/*
* iterate over all the transfers completed by the engine,
* except for the last (i.e. use > instead of >=).
*/
while (transfer && (!transfer->cyclic) &&
(*pdesc_completed > transfer->desc_num)) {
/* remove this transfer from pdesc_completed */
*pdesc_completed -= transfer->desc_num;
dbg_tfr("%s engine completed non-cyclic xfer 0x%p (%d desc)\n",
engine->name, transfer, transfer->desc_num);
/* remove completed transfer from list */
list_del(engine->transfer_list.next);
/* add to dequeued number of descriptors during this run */
engine->desc_dequeued += transfer->desc_num;
/* mark transfer as succesfully completed */
transfer->state = TRANSFER_STATE_COMPLETED;
/* Complete transfer - sets transfer to NULL if an async
* transfer has completed */
transfer = engine_transfer_completion(engine, transfer);
/* if exists, get the next transfer on the list */
if (!list_empty(&engine->transfer_list)) {
transfer = list_entry(engine->transfer_list.next,
struct xdma_transfer, entry);
dbg_tfr("Non-completed transfer %p\n", transfer);
} else {
/* no further transfers? */
transfer = NULL;
}
}
return transfer;
}
static void engine_err_handle(struct xdma_engine *engine,
struct xdma_transfer *transfer, u32 desc_completed)
{
u32 value;
/*
* The BUSY bit is expected to be clear now but older HW has a race
* condition which could cause it to be still set. If it's set, re-read
* and check again. If it's still set, log the issue.
*/
if (engine->status & XDMA_STAT_BUSY) {
value = read_register(&engine->regs->status);
if ((value & XDMA_STAT_BUSY) && printk_ratelimit())
pr_info("%s has errors but is still BUSY\n",
engine->name);
}
if (printk_ratelimit()) {
pr_info("%s, s 0x%x, aborted xfer 0x%p, cmpl %d/%d\n",
engine->name, engine->status, transfer, desc_completed,
transfer->desc_num);
}
/* mark transfer as failed */
transfer->state = TRANSFER_STATE_FAILED;
xdma_engine_stop(engine);
}
struct xdma_transfer *engine_service_final_transfer(struct xdma_engine *engine,
struct xdma_transfer *transfer, u32 *pdesc_completed)
{
BUG_ON(!engine);
BUG_ON(!pdesc_completed);
/* inspect the current transfer */
if (unlikely(!transfer)) {
pr_info("%s xfer empty, pdesc completed %u.\n",
engine->name, *pdesc_completed);
return NULL;
} else {
if (((engine->dir == DMA_FROM_DEVICE) &&
(engine->status & XDMA_STAT_C2H_ERR_MASK)) ||
((engine->dir == DMA_TO_DEVICE) &&
(engine->status & XDMA_STAT_H2C_ERR_MASK))) {
pr_info("engine %s, status error 0x%x.\n",
engine->name, engine->status);
engine_status_dump(engine);
engine_err_handle(engine, transfer, *pdesc_completed);
goto transfer_del;
}
if (engine->status & XDMA_STAT_BUSY)
pr_debug("engine %s is unexpectedly busy - ignoring\n",
engine->name);
/* the engine stopped on current transfer? */
if (*pdesc_completed < transfer->desc_num) {
transfer->state = TRANSFER_STATE_FAILED;
pr_info("%s, xfer 0x%p, stopped half-way, %d/%d.\n",
engine->name, transfer, *pdesc_completed,
transfer->desc_num);
} else {
dbg_tfr("engine %s completed transfer\n", engine->name);
dbg_tfr("Completed transfer ID = 0x%p\n", transfer);
dbg_tfr("*pdesc_completed=%d, transfer->desc_num=%d",
*pdesc_completed, transfer->desc_num);
if (!transfer->cyclic) {
/*
* if the engine stopped on this transfer,
* it should be the last
*/
WARN_ON(*pdesc_completed > transfer->desc_num);
}
/* mark transfer as succesfully completed */
transfer->state = TRANSFER_STATE_COMPLETED;
}
transfer_del:
/* remove completed transfer from list */
list_del(engine->transfer_list.next);
/* add to dequeued number of descriptors during this run */
engine->desc_dequeued += transfer->desc_num;
/*
* Complete transfer - sets transfer to NULL if an asynchronous
* transfer has completed
*/
transfer = engine_transfer_completion(engine, transfer);
}
return transfer;
}
#ifdef INTERNAL_TESTING
static void engine_service_perf(struct xdma_engine *engine, u32 desc_completed)
{
BUG_ON(!engine);
/* performance measurement is running? */
if (engine->xdma_perf) {
/* a descriptor was completed? */
if (engine->status & XDMA_STAT_DESC_COMPLETED) {
engine->xdma_perf->iterations = desc_completed;
dbg_perf("transfer->xdma_perf->iterations=%d\n",
engine->xdma_perf->iterations);
}
/* a descriptor stopped the engine? */
if (engine->status & XDMA_STAT_DESC_STOPPED) {
engine->xdma_perf->stopped = 1;
/*
* wake any XDMA_PERF_IOCTL_STOP waiting for
* the performance run to finish
*/
wake_up_interruptible(&engine->xdma_perf_wq);
dbg_perf("transfer->xdma_perf stopped\n");
}
}
}
#endif
static void engine_transfer_dequeue(struct xdma_engine *engine)
{
struct xdma_transfer *transfer;
BUG_ON(!engine);
/* pick first transfer on the queue (was submitted to the engine) */
transfer = list_entry(engine->transfer_list.next, struct xdma_transfer,
entry);
if (!transfer || transfer != &engine->cyclic_req->xfer) {
pr_info("%s, xfer 0x%p != 0x%p.\n",
engine->name, transfer, &engine->cyclic_req->xfer);
return;
}
dbg_tfr("%s engine completed cyclic transfer 0x%p (%d desc).\n",
engine->name, transfer, transfer->desc_num);
/* remove completed transfer from list */
list_del(engine->transfer_list.next);
}
static int engine_ring_process(struct xdma_engine *engine)
{
struct xdma_result *result;
int start;
int eop_count = 0;
BUG_ON(!engine);
result = engine->cyclic_result;
BUG_ON(!result);
/* where we start receiving in the ring buffer */
start = engine->rx_tail;
/* iterate through all newly received RX result descriptors */
dbg_tfr("%s, result %d, 0x%x, len 0x%x.\n",
engine->name, engine->rx_tail, result[engine->rx_tail].status,
result[engine->rx_tail].length);
while (result[engine->rx_tail].status && !engine->rx_overrun) {
/* EOP bit set in result? */
if (result[engine->rx_tail].status & RX_STATUS_EOP){
eop_count++;
}
/* increment tail pointer */
engine->rx_tail = (engine->rx_tail + 1) % CYCLIC_RX_PAGES_MAX;
dbg_tfr("%s, head %d, tail %d, 0x%x, len 0x%x.\n",
engine->name, engine->rx_head, engine->rx_tail,
result[engine->rx_tail].status,
result[engine->rx_tail].length);
/* overrun? */
if (engine->rx_tail == engine->rx_head) {
dbg_tfr("%s: overrun\n", engine->name);
/* flag to user space that overrun has occurred */
engine->rx_overrun = 1;
}
}
return eop_count;
}
static int engine_service_cyclic_polled(struct xdma_engine *engine)
{
int eop_count = 0;
int rc = 0;
struct xdma_poll_wb *writeback_data;
u32 sched_limit = 0;
BUG_ON(!engine);
BUG_ON(engine->magic != MAGIC_ENGINE);
writeback_data = (struct xdma_poll_wb *)engine->poll_mode_addr_virt;
while (eop_count == 0) {
if (sched_limit != 0) {
if ((sched_limit % NUM_POLLS_PER_SCHED) == 0)
schedule();
}
sched_limit++;
/* Monitor descriptor writeback address for errors */
if ((writeback_data->completed_desc_count) & WB_ERR_MASK) {
rc = -1;
break;
}
eop_count = engine_ring_process(engine);
}
if (eop_count == 0) {
engine_status_read(engine, 1, 0);
if ((engine->running) && !(engine->status & XDMA_STAT_BUSY)) {
/* transfers on queue? */
if (!list_empty(&engine->transfer_list))
engine_transfer_dequeue(engine);
engine_service_shutdown(engine);
}
}
return rc;
}
static int engine_service_cyclic_interrupt(struct xdma_engine *engine)
{
int eop_count = 0;
struct xdma_transfer *xfer;
BUG_ON(!engine);
BUG_ON(engine->magic != MAGIC_ENGINE);
engine_status_read(engine, 1, 0);
eop_count = engine_ring_process(engine);
/*
* wake any reader on EOP, as one or more packets are now in
* the RX buffer
*/
xfer = &engine->cyclic_req->xfer;
if(enable_credit_mp){
if (eop_count > 0) {
//engine->eop_found = 1;
}
wake_up_interruptible(&xfer->wq);
}else{
if (eop_count > 0) {
/* awake task on transfer's wait queue */
dbg_tfr("wake_up_interruptible() due to %d EOP's\n", eop_count);
engine->eop_found = 1;
wake_up_interruptible(&xfer->wq);