From eed38a8a0f2c7a00225cd97fb9a556e8fba2b504 Mon Sep 17 00:00:00 2001 From: yuguen-intel Date: Mon, 21 Mar 2022 21:31:32 +0100 Subject: [PATCH] FPGA QRD seed update (#894) * update qrd seeds to meet 2022.2 target Signed-off-by: Yohann Uguen * Updating seeds for 2022.2 --- .../DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt index 0f12aef7ba..12ad7441e1 100755 --- a/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt +++ b/DirectProgramming/DPC++FPGA/ReferenceDesigns/qrd/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(FPGA_BOARD MATCHES ".*a10.*") set(COMPLEX 1) set(FIXED_ITERATIONS 64) set(CLOCK_TARGET 360MHz) - set(SEED "-Xsseed=5") + set(SEED "-Xsseed=26") elseif(FPGA_BOARD MATCHES ".*s10.*") # S10 parameters set(ROWS_COMPONENT 256) @@ -40,7 +40,7 @@ elseif(FPGA_BOARD MATCHES ".*s10.*") set(COMPLEX 1) set(FIXED_ITERATIONS 110) set(CLOCK_TARGET 480MHz) - set(SEED "-Xsseed=5") + set(SEED "-Xsseed=4") elseif(FPGA_BOARD MATCHES ".*agilex.*") # Agilex™ parameters set(ROWS_COMPONENT 256)