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Copy pathSRAM_hw.tcl
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SRAM_hw.tcl
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# TCL File Generated by Component Editor 11.0sp1
# Wed Jul 04 20:28:28 EDT 2012
# DO NOT MODIFY
# +-----------------------------------
# |
# | SRAM "SRAM DE1" v1.0
# | Jean Charles Vallieres 2012.07.04.20:28:28
# | SRAM controller for DE1 board
# |
# | D:/dev/gbfpga/SRAM.vhd
# |
# | ./SRAM.vhd syn, sim
# |
# +-----------------------------------
# +-----------------------------------
# | request TCL package from ACDS 11.0
# |
package require -exact sopc 11.0
# |
# +-----------------------------------
# +-----------------------------------
# | module SRAM
# |
set_module_property DESCRIPTION "SRAM controller for DE1 board"
set_module_property NAME SRAM
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Memories and Memory Controllers/External Memory Interfaces/Memory Interfaces"
set_module_property AUTHOR "Jean Charles Vallieres"
set_module_property DISPLAY_NAME "SRAM DE1"
set_module_property TOP_LEVEL_HDL_FILE SRAM.vhd
set_module_property TOP_LEVEL_HDL_MODULE sram_ctrl
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property ANALYZE_HDL TRUE
set_module_property STATIC_TOP_LEVEL_MODULE_NAME sram_ctrl
set_module_property FIX_110_VIP_PATH false
# |
# +-----------------------------------
# +-----------------------------------
# | files
# |
add_file SRAM.vhd {SYNTHESIS SIMULATION}
# |
# +-----------------------------------
# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------
# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------
# +-----------------------------------
# | connection point clock
# |
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
add_interface_port clock clk clk Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point avalon_slave_0
# |
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 addressUnits WORDS
set_interface_property avalon_slave_0 associatedClock clock
set_interface_property avalon_slave_0 associatedReset reset_sink
set_interface_property avalon_slave_0 bitsPerSymbol 8
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 burstcountUnits WORDS
set_interface_property avalon_slave_0 explicitAddressSpan 0
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 readLatency 1
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 ENABLED true
add_interface_port avalon_slave_0 write write Input 1
add_interface_port avalon_slave_0 waitrequest waitrequest Output 1
add_interface_port avalon_slave_0 address address Input 18
add_interface_port avalon_slave_0 readdata readdata Output 16
add_interface_port avalon_slave_0 writedata writedata Input 16
add_interface_port avalon_slave_0 byteenable byteenable Input 2
add_interface_port avalon_slave_0 read read Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point reset_sink
# |
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
add_interface_port reset_sink rst_n reset_n Input 1
# |
# +-----------------------------------
# +-----------------------------------
# | connection point conduit_end
# |
add_interface conduit_end conduit end
set_interface_property conduit_end ENABLED true
add_interface_port conduit_end sram_ce_n export Output 1
add_interface_port conduit_end sram_addr export Output 18
add_interface_port conduit_end sram_dq export Bidir 16
add_interface_port conduit_end sram_oe_n export Output 1
add_interface_port conduit_end sram_ub_n export Output 1
add_interface_port conduit_end sram_lb_n export Output 1
add_interface_port conduit_end sram_we_n export Output 1
# |
# +-----------------------------------