Here are some mplementations of some basic hardware units in RTL language (verilog for now), which can be used for area/power evaluation and support the hardware design tradeoff.
- mux:
- arithmetic_units:
- systolic_array: xinhao
- tensor_core: jun
- mac_tree: hongyi
- vector_alu: hongyi
- bitonic_sorting: chiyue
- prefix_sum: kai
- fan: kai
- mrn:
- merge_tree:
- cross_bar:
- benes_network:
Create the repo.
Add original files of these modules:
- systolic_array: xinhao
- tensor_core: jun
- mac_tree: hongyi
- vector_alu: hongyi
- bitonic_sorting: chiyue
- prefix_sum: kai
- fan: kai
Organize the code style. Clearify the file structure, input, output, function defination, parameter of each module in code file and readme document. Make the plan of parameterize these modules.
Make each module parameterized, both in code and document.