From 79cf67e96427637e1c3573efcd6167eb89c96d72 Mon Sep 17 00:00:00 2001 From: steward-fu Date: Fri, 10 Jan 2025 07:37:52 +0800 Subject: [PATCH] Added STEP-MAX10 V1 support. --- doc/FPGAs.yml | 2 +- doc/boards.yml | 7 +++++++ src/board.hpp | 3 ++- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/doc/FPGAs.yml b/doc/FPGAs.yml index 5dde97c818..8582f8a680 100644 --- a/doc/FPGAs.yml +++ b/doc/FPGAs.yml @@ -136,7 +136,7 @@ Intel: Flash: OK - Description: Max 10 - Model: 10M08 + Model: 10M02, 10M08 URL: https://www.intel.fr/content/www/fr/fr/products/details/fpga/max/10.html Memory: SVF Flash: POF diff --git a/doc/boards.yml b/doc/boards.yml index 1da46b6b76..00ff2ec603 100644 --- a/doc/boards.yml +++ b/doc/boards.yml @@ -995,3 +995,10 @@ FPGA: Titanium Ti180J484 (and others) Memory: OK Flash: NA + +- ID: step-max10_v1 + Description: STEP MAX10 V1 + URL: https://wiki.stepfpga.com/step-max10 + FPGA: Altera 10M02SCM153C8G + Memory: OK + Flash: NA diff --git a/src/board.hpp b/src/board.hpp index 04763f5eca..1f3cb52808 100644 --- a/src/board.hpp +++ b/src/board.hpp @@ -253,7 +253,8 @@ static std::map board_list = { JTAG_BOARD("zybo_z7_10", "xc7z010clg400", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("zybo_z7_20", "xc7z020clg400", "digilent", 0, 0, CABLE_DEFAULT), JTAG_BOARD("mini_itx", "xc7z100ffg900", "jtag-smt2-nc", 0, 0, CABLE_DEFAULT), - JTAG_BOARD("vmm3", "xc7s50csga324", "ft2232", 0, 0, CABLE_DEFAULT) + JTAG_BOARD("vmm3", "xc7s50csga324", "ft2232", 0, 0, CABLE_DEFAULT), + JTAG_BOARD("step-max10_v1", "10m02scm153c8g", "usb-blaster",0, 0, CABLE_DEFAULT) }; #endif