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v0.1.0 (planned to ship in 4th December 2017)

Goals:

• adding v0.1.0 tag
• adding possibility to work with logic utilities without requiring some 3rd parties tools and libraries
• ModelSim - should be optional, all modelsim-* targets won't be created, unit tests that use ModelSim will be skipped
• Quartus - should be optional, all quartus-* targets won't be created
• Natural Docs - should be optional, no possibility to create documentation
• adding Open Verification Library (OVL) to project
• adding OVL assertions in some SystemVerilog interfaces and modules
• adding support for Xilinx Vivado similar to Intel FPGA Quartus analysis and elaboration
• adding remaining source code documentation for C++ and SystemVerilog using Natural Docs
• extending documentations about logic (doc/*.md)
• extending UVM-SystemC unit test examples with overriding sequences and scoreboards
• point to external project repository that use logic