From 834ff4544a5ce398027930d5c4d5a81f82f30098 Mon Sep 17 00:00:00 2001 From: chick Date: Wed, 25 Oct 2017 18:54:45 -0700 Subject: [PATCH] Update node widths with Firrtl Transform Working transform that will adjust widths of registers, ports and wires through the annotation system. Second piece of the augmented tool chain that will ultimately take advantage of firrt interpreters instrumentation output. Adjusting widths according to data gathered thereby. Part of Issue #114 --- .../dsptools/numbers/resizer/ChangeWidthTransform.scala | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/main/scala/dsptools/numbers/resizer/ChangeWidthTransform.scala b/src/main/scala/dsptools/numbers/resizer/ChangeWidthTransform.scala index 9c923034..b5ce79bb 100644 --- a/src/main/scala/dsptools/numbers/resizer/ChangeWidthTransform.scala +++ b/src/main/scala/dsptools/numbers/resizer/ChangeWidthTransform.scala @@ -68,11 +68,6 @@ class ChangeWidthTransform extends Transform with LazyLogging { changeRequests.contains(name) } - def annotationToWidth(annotation: Annotation): Width = { - //TODO (chick) complete this - IntWidth(32) - } - def changeWidthsInExpression(expression: Expression): Expression = { expression }