diff --git a/libs/librrgraph/src/base/rr_graph_view.h b/libs/librrgraph/src/base/rr_graph_view.h index 60f03a4b7e0..d0fffc04307 100644 --- a/libs/librrgraph/src/base/rr_graph_view.h +++ b/libs/librrgraph/src/base/rr_graph_view.h @@ -345,7 +345,7 @@ class RRGraphView { coordinate_string += " length:" + std::to_string(node_length(node)); //add the length of the segment //Figure out the starting and ending coordinate of the segment depending on the direction - arrow = "->"; //we will point the coordinates from start to finish, left to right + arrow = " ->"; //we will point the coordinates from start to finish, left to right if (node_direction(node) == Direction::DEC) { //signal travels along decreasing direction @@ -365,7 +365,7 @@ class RRGraphView { end_y = std::to_string(node_yhigh(node)) + ","; end_layer_str = std::to_string(node_layer_num) + ")"; //layer number if (node_direction(node) == Direction::BIDIR) { - arrow = "<->"; //indicate that signal can travel both direction + arrow = " <->"; //indicate that signal can travel both direction } } } diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index b0193ea52c3..282f717c0dd 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -550,10 +550,10 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, buffered, fan_in_list); if (num_switches == 0) { - VTR_LOG_WARN("Node: %d with RR_type: %s at Location:%s, had no out-going switches\n", rr_id, + VTR_LOG_WARN("Node: %d with RR_type: %s at Location:%s, had no incoming switches\n", rr_id, rr_graph.node_type_string(rr_id), node_cords.c_str()); continue; - } + } VTR_ASSERT(num_switches > 0); num_nodes_of_index[cost_index]++; diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 369da62a7f7..a542e58000e 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -256,7 +256,7 @@ static void report_overused_ipin_opin(std::ostream& os, //Print out the block index, name and type // TODO: Needs to be updated when RR Graph Nodes know their layer_num - ClusterBlockId block_id = grid_info.block_at_location({grid_x, grid_y, isubtile, 0}); + ClusterBlockId block_id = grid_info.block_at_location({grid_x, grid_y, isubtile, grid_layer}); os << "Block #" << iblock << ": "; os << "Block name = " << clb_nlist.block_pb(block_id)->name << ", "; os << "Block type = " << clb_nlist.block_type(block_id)->name << '\n'; diff --git a/vpr/src/route/router_lookahead_map.cpp b/vpr/src/route/router_lookahead_map.cpp index 80cac91ee16..88cd75d46c8 100644 --- a/vpr/src/route/router_lookahead_map.cpp +++ b/vpr/src/route/router_lookahead_map.cpp @@ -330,11 +330,23 @@ std::pair MapLookahead::get_expected_delay_and_cong(RRNodeId from_ auto from_ptc = rr_graph.node_ptc_num(from_node); - std::tie(expected_delay_cost, expected_cong_cost) = util::get_cost_from_src_opin(src_opin_delays[from_layer_num][from_tile_index][from_ptc][to_layer_num], - delta_x, - delta_y, - to_layer_num, - get_wire_cost_entry); + /* We could reach the sink by using an intermediate wire on any reachable layer. We consider all these options and return the minimum cost one. + * get_cost_from_src_opin iterates over all routing segments passed to it (the first argument) and returns + * the minimum cost among them. In the following for loop, we iterate over each layer and pass it the + * routing segments on that layer reachable from the OPIN/SOURCE to segments on that layer. This for loop then calculates and returns + * the minimum cost from the given OPIN/SOURCE to the specified SINK considering routing options across all layers. + */ + for (int layer_num = 0; layer_num < device_ctx.grid.get_num_layers(); layer_num++) { + float this_delay_cost; + float this_cong_cost; + std::tie(this_delay_cost, this_cong_cost) = util::get_cost_from_src_opin(src_opin_delays[from_layer_num][from_tile_index][from_ptc][layer_num], + delta_x, + delta_y, + to_layer_num, + get_wire_cost_entry); + expected_delay_cost = std::min(expected_delay_cost, this_delay_cost); + expected_cong_cost = std::min(expected_cong_cost, this_cong_cost); + } expected_delay_cost *= params.criticality; expected_cong_cost *= (1 - params.criticality); diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_auto_bb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_auto_bb/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_auto_bb/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/config.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/config.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/config.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt similarity index 100% rename from vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/golden_results.txt rename to vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb/config/golden_results.txt diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/config.txt new file mode 100644 index 00000000000..84cc7f3969b --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/config.txt @@ -0,0 +1,52 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of SDC files +sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/multi_die/stratixiv_3d + +# Add circuits to list to sweep +circuit_list_add=carpat_stratixiv_arch_timing.blif +circuit_list_add=CH_DFSIN_stratixiv_arch_timing.blif +circuit_list_add=CHERI_stratixiv_arch_timing.blif +circuit_list_add=EKF-SLAM_Jacobians_stratixiv_arch_timing.blif +circuit_list_add=fir_cascade_stratixiv_arch_timing.blif +circuit_list_add=jacobi_stratixiv_arch_timing.blif +circuit_list_add=JPEG_stratixiv_arch_timing.blif +circuit_list_add=leon2_stratixiv_arch_timing.blif +circuit_list_add=leon3mp_stratixiv_arch_timing.blif +circuit_list_add=MCML_stratixiv_arch_timing.blif +circuit_list_add=MMM_stratixiv_arch_timing.blif +circuit_list_add=radar20_stratixiv_arch_timing.blif +circuit_list_add=random_stratixiv_arch_timing.blif +circuit_list_add=Reed_Solomon_stratixiv_arch_timing.blif +circuit_list_add=smithwaterman_stratixiv_arch_timing.blif +circuit_list_add=stap_steering_stratixiv_arch_timing.blif +circuit_list_add=sudoku_check_stratixiv_arch_timing.blif +circuit_list_add=SURF_desc_stratixiv_arch_timing.blif +circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif +circuit_list_add=uoft_raytracer_stratixiv_arch_timing.blif +circuit_list_add=wb_conmax_stratixiv_arch_timing.blif +circuit_list_add=picosoc_stratixiv_arch_timing.blif +circuit_list_add=murax_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --custom_3d_sb_fanin_fanout 60 --router_lookahead map \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt new file mode 100644 index 00000000000..1ab11fa8780 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb/config/golden_results.txt @@ -0,0 +1,24 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 520.61 vpr 1.72 GiB 274 987 36 59 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1803496 22 252 53001 29054 7 24609 1358 54 40 4320 DSP auto 1204.1 MiB 39.90 216521 888364 256649 520395 111320 1761.2 MiB 87.85 0.71 7.67021 -36041.3 -6.67021 3.10875 0.08 0.126381 0.112882 16.7124 14.1733 342154 13.9217 83084 3.38056 76883 151222 326194146 106749769 0 0 8.89497e+07 20590.2 56 1365594 16211305 -1 9.14969 3.16574 -43836.7 -8.14969 0 0 32.91 -1 -1 1761.2 MiB 138.38 31.7678 27.6452 1761.2 MiB -1 194.50 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 417.34 vpr 1.50 GiB 36 1580 10 10 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1572468 3 33 48977 39238 1 26329 1636 40 30 2400 LAB auto 1223.7 MiB 106.33 249698 955600 281109 638361 36130 1458.1 MiB 103.12 1.05 82.0766 -56743.3 -81.0766 82.0766 0.04 0.11202 0.0959451 12.7886 10.3669 398272 15.1290 101546 3.85740 95740 256181 200343144 42868641 0 0 4.91306e+07 20471.1 44 758110 8921656 -1 71.392 71.392 -126837 -70.392 0 0 18.37 -1 -1 1481.7 MiB 63.81 24.8111 20.6403 1458.1 MiB -1 98.71 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 888.33 vpr 1.97 GiB 211 2261 3 210 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2062840 38 173 62892 59064 3 35566 2685 60 44 5280 M9K auto 1410.9 MiB 217.72 478758 1942701 680573 1218059 44069 2014.5 MiB 176.36 1.51 11.7665 -297024 -10.7665 7.51698 0.09 0.202619 0.16947 25.2532 19.6817 772503 21.7245 195521 5.49850 143008 511949 475300762 109106753 0 0 1.08858e+08 20617.0 56 1675578 19868374 -1 14.2505 7.86617 -385289 -13.2505 0 0 41.27 -1 -1 2014.5 MiB 166.71 50.776 41.2384 2014.5 MiB -1 244.64 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1114.78 vpr 1.92 GiB 574 2772 16 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2014640 4 570 66175 54803 2 39317 3362 51 38 3876 LAB auto 1449.1 MiB 196.88 499724 2671912 950738 1625402 95772 1861.6 MiB 224.11 1.77 27.5032 -105534 -26.5032 5.41511 0.06 0.199192 0.172892 26.8354 21.1953 803998 20.4517 200370 5.09692 177923 701320 1281304364 359064468 0 0 7.97022e+07 20563.0 20 1225854 14507865 -1 30.2412 6.45869 -119451 -29.2412 0 0 29.13 -1 -1 1864.8 MiB 453.83 38.7043 31.5496 1861.6 MiB -1 172.45 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 2049.90 vpr 4.79 GiB 40 3678 172 1 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5023844 19 21 171111 96274 1 73063 3891 129 96 24768 DSP auto 1882.9 MiB 124.90 684201 3735993 1501648 2208285 26060 4906.1 MiB 148.94 1.66 6.00962 -98830.8 -5.00962 3.45872 0.32 0.391796 0.341532 49.21 43.1537 833239 11.4049 184319 2.52284 146193 177078 507711122 213695314 0 0 5.14406e+08 20769.0 13 7758968 93673935 -1 5.92189 4.22813 -137430 -4.92189 0 0 182.05 -1 -1 4906.1 MiB 207.32 64.5253 57.3404 4906.1 MiB -1 1108.11 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 514.96 vpr 1.64 GiB 536 1953 7 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1718304 227 309 49176 40422 1 28164 2500 47 35 3290 io auto 1277.5 MiB 147.28 266723 1918980 725646 1136427 56907 1646.8 MiB 121.43 1.12 194.338 -109756 -193.338 194.338 0.06 0.111355 0.0960834 15.0867 12.0805 409856 14.5545 103143 3.66275 87257 277955 172520127 35585678 0 0 6.75216e+07 20523.3 21 1033138 12274942 -1 196.949 196.949 -148256 -195.949 0 0 25.10 -1 -1 1646.8 MiB 48.56 22.5017 18.5228 1646.8 MiB -1 139.81 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 637.08 vpr 1.80 GiB 36 1342 8 149 2 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1888764 3 33 52402 39411 1 28062 1537 57 42 4788 M9K auto 1243.0 MiB 103.75 273842 834941 243386 565684 25871 1844.5 MiB 86.68 0.82 15.7112 -289050 -14.7112 15.7112 0.08 0.119058 0.102615 13.4566 10.7905 420305 14.9820 105404 3.75718 100360 260743 546160418 129480870 0 0 9.85096e+07 20574.3 31 1507654 17957159 -1 18.1236 18.1236 -347845 -17.1236 0 0 36.57 -1 -1 1844.5 MiB 161.91 23.1123 19.1485 1844.5 MiB -1 216.44 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 204.89 vpr 1.28 GiB 251 954 1 17 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1341080 55 196 20131 19956 1 8282 1223 32 24 1536 LAB auto 1088.4 MiB 66.85 105468 576479 179756 366623 30100 1309.6 MiB 23.08 0.27 7.56709 -65136 -6.56709 7.56709 0.02 0.0500856 0.0384976 4.85645 3.72985 179329 21.6607 46312 5.59391 29504 122672 72003745 13823732 0 0 3.14199e+07 20455.7 25 483264 5705245 -1 8.81703 8.81703 -85275.7 -7.81703 0 0 12.37 -1 -1 1309.6 MiB 22.42 8.31826 6.6994 1309.6 MiB -1 59.44 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 589.98 vpr 1.54 GiB 255 2123 1 28 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1610260 84 171 36458 36247 3 20352 2407 45 33 2970 LAB auto 1231.2 MiB 174.99 241376 1598683 558192 952375 88116 1542.8 MiB 73.08 0.66 10.1083 -70133.7 -9.1083 4.12508 0.04 0.115981 0.0878 12.7489 9.8058 400083 19.6717 97548 4.79634 61046 216519 401222983 118385406 0 0 6.09438e+07 20519.8 15 935204 11078823 -1 12.436 4.7257 -87531.4 -11.436 0 0 22.73 -1 -1 1542.8 MiB 163.43 18.4518 14.7362 1542.8 MiB -1 127.22 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 876.17 vpr 2.42 GiB 69 2107 10 295 16 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2536200 36 33 57796 49182 1 20334 2497 79 59 9322 M144K auto 1353.5 MiB 112.44 207195 2136055 812529 1275642 47884 2476.8 MiB 85.13 0.73 8.88006 -82826.8 -7.88006 8.88006 0.14 0.117618 0.0988504 16.8798 13.4801 387054 19.0395 94434 4.64529 67787 213274 284083043 79148811 0 0 1.92002e+08 20596.6 76 2917968 35039980 -1 10.009 10.009 -164810 -9.00897 0 0 68.45 -1 -1 2476.8 MiB 114.92 38.9885 32.6103 2476.8 MiB -1 446.62 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 736.20 vpr 2.14 GiB 478 1231 1 300 4 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2247640 202 276 35125 30509 3 21728 2014 73 54 7884 M9K auto 1187.1 MiB 97.40 215797 1654704 587326 990918 76460 2195.0 MiB 74.14 0.51 9.19228 -26875.5 -8.19228 3.05134 0.12 0.118753 0.0925985 16.8246 13.1399 376974 17.3545 88484 4.07347 60418 171331 292439604 76641418 0 0 1.62738e+08 20641.5 20 2479452 29744051 -1 9.3155 3.44252 -47330.5 -8.3155 0 0 58.40 -1 -1 2195.0 MiB 100.36 23.6255 19.1348 2195.0 MiB -1 368.29 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 284.11 vpr 1.46 GiB 5 330 31 105 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1535704 3 2 14862 10304 26 7620 473 49 36 3528 DSP auto 1034.8 MiB 49.27 92588 153359 38791 100501 14067 1499.7 MiB 8.95 0.10 5.67702 -19552.3 -4.67702 3.79963 0.05 0.0467277 0.0410877 4.49584 3.7966 163693 21.5556 38186 5.02844 20395 46106 86292972 21661805 0 0 7.26079e+07 20580.5 24 1120110 13214470 -1 5.87594 4.15929 -36105.4 -4.87594 0 0 26.89 -1 -1 1499.7 MiB 26.95 7.94052 6.90757 1499.7 MiB -1 151.30 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 569.26 vpr 1.82 GiB 693 1777 25 16 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1904396 35 658 51416 37539 1 27463 2511 58 43 4988 io auto 1278.1 MiB 99.65 212181 2083831 717693 1222429 143709 1859.8 MiB 106.25 0.84 40.5037 -60224.2 -39.5037 40.5037 0.09 0.128488 0.113425 18.2416 14.9291 330278 12.7260 81833 3.15312 94649 304701 197817782 44987282 0 0 1.02587e+08 20566.7 26 1568252 18700371 -1 39.261 39.261 -66616.1 -38.2609 0 0 38.02 -1 -1 1859.8 MiB 59.17 27.948 23.4447 1859.8 MiB -1 230.32 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 470.62 vpr 1.83 GiB 753 1108 5 32 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1915540 13 740 25173 25306 1 12781 1898 63 47 5922 io auto 1130.4 MiB 71.87 124962 1223482 428622 736669 58191 1870.6 MiB 40.32 0.32 8.57799 -25886.9 -7.57799 8.57799 0.09 0.0666816 0.0576129 8.22186 6.71409 184141 14.4153 45279 3.54462 32905 123041 47256325 10410499 0 0 1.22008e+08 20602.6 29 1871156 22275272 -1 8.85683 8.47371 -35058.8 -7.85683 0 0 44.24 -1 -1 1870.6 MiB 19.02 13.7447 11.5422 1870.6 MiB -1 265.30 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 665.26 vpr 1.70 GiB 117 2173 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1780732 79 38 66795 54922 1 36442 2290 46 34 3128 LAB auto 1332.5 MiB 118.39 223170 1465826 438868 989440 37518 1631.4 MiB 116.51 1.00 10.0034 -164441 -9.00345 10.0034 0.05 0.140615 0.10816 15.3551 12.0225 328872 9.02528 85242 2.33931 156751 378493 614757965 143147538 0 0 6.41689e+07 20514.4 66 983570 11662836 -1 10.4048 10.4048 -200702 -9.40483 0 0 23.96 -1 -1 1655.2 MiB 233.33 36.8481 30.0419 1631.4 MiB -1 139.49 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 407.83 vpr 1.66 GiB 213 1565 26 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1737656 139 74 57121 41054 1 24175 1808 49 36 3528 DSP auto 1290.3 MiB 89.57 147265 1212908 383568 790816 38524 1687.9 MiB 69.62 0.60 5.18803 -15564.9 -4.18803 4.69751 0.06 0.132355 0.115165 16.3281 13.6684 218052 9.02122 54686 2.26246 53635 97635 86433611 24558382 0 0 7.26079e+07 20580.5 22 1120110 13214470 -1 5.61308 5.61308 -32689.4 -4.61308 0 0 26.73 -1 -1 1687.9 MiB 33.82 24.3867 20.8618 1687.9 MiB -1 158.29 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 207.60 vpr 1.26 GiB 54 659 0 40 0 1 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1323644 2 52 16673 16662 2 12066 754 32 24 1536 M9K auto 1066.2 MiB 53.44 154124 275154 74667 179945 20542 1292.6 MiB 19.41 0.22 5.39679 -16155.6 -4.39679 4.49872 0.02 0.0602811 0.0465091 5.32106 4.24475 238163 19.7449 63975 5.30385 56894 169908 152382564 31381158 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.73871 5.3677 -26489.1 -5.73871 0 0 11.94 -1 -1 1292.6 MiB 44.16 8.78802 7.31639 1292.6 MiB -1 58.83 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 633.14 vpr 1.77 GiB 445 2151 19 52 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1857528 131 314 57881 45152 1 32955 2667 49 36 3528 DSP auto 1363.0 MiB 124.71 294607 2054724 754821 1217361 82542 1716.5 MiB 175.07 1.59 191.584 -64615.7 -190.584 191.584 0.05 0.18745 0.150512 23.6039 19.2336 445934 13.5621 110207 3.35169 137218 430293 351839984 68634033 0 0 7.26079e+07 20580.5 40 1120110 13214470 -1 199.253 199.253 -80683.6 -198.253 0 0 29.02 -1 -1 1733.2 MiB 107.66 40.3599 33.6861 1716.5 MiB -1 162.17 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 100.48 vpr 1.19 GiB 42 752 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1244324 13 29 26295 20086 1 12509 794 29 21 1218 LAB auto 1062.8 MiB 15.76 62891 261719 56222 191052 14445 1215.2 MiB 11.16 0.13 4.85572 -4225.92 -3.85572 2.52096 0.02 0.0230785 0.0193446 2.10304 1.7256 79797 6.38019 22463 1.79603 26933 37992 38420451 7963787 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 5.10516 2.8003 -5630 -4.10516 0 0 9.38 -1 -1 1215.2 MiB 10.20 3.46483 2.94414 1215.2 MiB -1 34.98 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 992.51 vpr 2.27 GiB 964 977 19 34 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2381124 542 422 37277 26038 1 20599 1994 78 58 9048 io auto 1149.6 MiB 66.87 226304 1519939 558967 890778 70194 2325.3 MiB 119.69 1.26 7.37113 -33408.8 -6.37113 7.37113 0.13 0.0952139 0.0773201 12.7243 10.3294 334343 16.2334 78109 3.79244 102458 238617 478712499 184281568 0 0 1.86852e+08 20651.1 60 2837414 34147767 -1 8.84853 8.84853 -42837.3 -7.84853 0 0 65.96 -1 -1 2325.3 MiB 257.74 25.311 21.3358 2325.3 MiB -1 442.74 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 841.75 vpr 2.52 GiB 1107 729 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2644060 403 704 15490 16194 1 8574 1836 88 65 11440 io auto 1060.4 MiB 54.40 122558 1384110 547152 796309 40649 2582.1 MiB 30.97 0.29 10.4549 -16402 -9.45487 4.73896 0.17 0.0533879 0.0433669 6.8282 5.61818 173895 20.2840 38605 4.50309 24038 94279 126191912 44771966 0 0 2.36204e+08 20647.2 14 3590540 43137666 -1 12.0851 5.88321 -24833.6 -11.0851 0 0 83.16 -1 -1 2582.1 MiB 63.98 9.36579 7.90327 2582.1 MiB -1 559.86 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.76 vpr 1.18 GiB 35 730 0 6 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1240184 18 17 16969 16357 1 6277 771 28 21 1176 LAB auto 1057.6 MiB 67.85 69205 265821 72177 187282 6362 1211.1 MiB 11.88 0.16 7.31748 -40693.1 -6.31748 7.31748 0.02 0.0306438 0.0257343 2.96374 2.35042 113779 18.1379 30059 4.79181 21341 106772 39406769 7295674 0 0 2.39639e+07 20377.5 31 369794 4343188 -1 8.79554 8.79554 -51620.5 -7.79554 0 0 8.95 -1 -1 1211.1 MiB 12.09 5.72142 4.74732 1211.1 MiB -1 40.12 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 29.75 vpr 994.02 MiB 35 73 0 8 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1017876 18 17 2291 2142 1 1500 116 13 10 260 LAB auto 953.8 MiB 7.30 9755 9704 1420 7286 998 994.0 MiB 0.48 0.01 5.28239 -3533.58 -4.28239 4.24487 0.00 0.00357156 0.00285794 0.176718 0.144844 15640 10.4476 4912 3.28123 4115 9431 4210567 862713 0 0 4.97530e+06 19135.8 17 75766 878809 -1 5.24221 4.56041 -4449.95 -4.24221 0 0 2.13 -1 -1 994.0 MiB 1.20 0.467896 0.409078 994.0 MiB -1 2.84 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/config.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/config.txt new file mode 100644 index 00000000000..7622b6922be --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/config.txt @@ -0,0 +1,52 @@ +# +############################################ +# Configuration file for running experiments +############################################## + +# Path to directory of circuits to use +circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of SDC files +sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv + +# Path to directory of architectures to use +archs_dir=arch/multi_die/stratixiv_3d + +# Add circuits to list to sweep +circuit_list_add=carpat_stratixiv_arch_timing.blif +circuit_list_add=CH_DFSIN_stratixiv_arch_timing.blif +circuit_list_add=CHERI_stratixiv_arch_timing.blif +circuit_list_add=EKF-SLAM_Jacobians_stratixiv_arch_timing.blif +circuit_list_add=fir_cascade_stratixiv_arch_timing.blif +circuit_list_add=jacobi_stratixiv_arch_timing.blif +circuit_list_add=JPEG_stratixiv_arch_timing.blif +circuit_list_add=leon2_stratixiv_arch_timing.blif +circuit_list_add=leon3mp_stratixiv_arch_timing.blif +circuit_list_add=MCML_stratixiv_arch_timing.blif +circuit_list_add=MMM_stratixiv_arch_timing.blif +circuit_list_add=radar20_stratixiv_arch_timing.blif +circuit_list_add=random_stratixiv_arch_timing.blif +circuit_list_add=Reed_Solomon_stratixiv_arch_timing.blif +circuit_list_add=smithwaterman_stratixiv_arch_timing.blif +circuit_list_add=stap_steering_stratixiv_arch_timing.blif +circuit_list_add=sudoku_check_stratixiv_arch_timing.blif +circuit_list_add=SURF_desc_stratixiv_arch_timing.blif +circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif +circuit_list_add=uoft_raytracer_stratixiv_arch_timing.blif +circuit_list_add=wb_conmax_stratixiv_arch_timing.blif +circuit_list_add=picosoc_stratixiv_arch_timing.blif +circuit_list_add=murax_stratixiv_arch_timing.blif + +# Add architectures to list to sweep +arch_list_add=3d_SB_inter_die_stratixiv_arch.timing.xml + +# Parse info and how to parse +parse_file=vpr_titan.txt + +# How to parse QoR info +qor_parse_file=qor_vpr_titan.txt + +# Pass requirements +pass_requirements_file=pass_requirements_vpr_titan.txt + +script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --custom_3d_sb_fanin_fanout 60 --place_bounding_box_mode per_layer_bb \ No newline at end of file diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt new file mode 100644 index 00000000000..0ab160efdd9 --- /dev/null +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb/config/golden_results.txt @@ -0,0 +1,24 @@ +arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error num_io num_LAB num_DSP num_M9K num_M144K num_PLL vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time routed_wirelength avg_routed_wirelength routed_wiresegment avg_routed_wiresegment total_nets_routed total_connections_routed total_heap_pushes total_heap_pops logic_block_area_total logic_block_area_used routing_area_total routing_area_per_tile crit_path_route_success_iteration num_rr_graph_nodes num_rr_graph_edges collapsed_nodes critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS create_rr_graph_time create_intra_cluster_rr_graph_time adding_internal_edges route_mem crit_path_route_time crit_path_total_timing_analysis_time crit_path_total_sta_time router_lookahead_mem tile_lookahead_computation_time router_lookahead_computation_time +3d_SB_inter_die_stratixiv_arch.timing.xml carpat_stratixiv_arch_timing.blif common 582.16 vpr 1.72 GiB 274 987 36 59 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1803524 22 252 53001 29054 7 24609 1358 54 40 4320 DSP auto 1204.1 MiB 42.52 195330 858296 247287 495125 115884 1761.3 MiB 84.93 0.67 7.80788 -36648 -6.80788 3.12522 0.08 0.124521 0.103496 15.0607 12.6449 371346 15.1095 103610 4.21573 80566 160946 461930857 165593977 0 0 8.89497e+07 20590.2 51 1365594 16211305 -1 8.74368 3.32525 -48171.4 -7.74368 0 0 32.76 -1 -1 1761.3 MiB 195.95 29.1002 25.2738 1761.3 MiB -1 198.81 +3d_SB_inter_die_stratixiv_arch.timing.xml CH_DFSIN_stratixiv_arch_timing.blif common 422.96 vpr 1.50 GiB 36 1580 10 10 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1573748 3 33 48977 39238 1 26329 1636 40 30 2400 LAB auto 1223.6 MiB 106.71 248841 888148 253476 594820 39852 1458.1 MiB 105.66 1.10 81.4784 -53835.8 -80.4784 81.4784 0.04 0.109711 0.0935788 11.8789 9.57793 411181 15.6194 116574 4.42826 92798 244546 220907410 47907010 0 0 4.91306e+07 20471.1 24 758110 8921656 -1 72.6227 72.6227 -121766 -71.6227 0 0 18.53 -1 -1 1483.2 MiB 63.69 19.757 16.3958 1458.1 MiB -1 101.16 +3d_SB_inter_die_stratixiv_arch.timing.xml CHERI_stratixiv_arch_timing.blif common 930.36 vpr 1.97 GiB 211 2261 3 210 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2062768 38 173 62892 59064 3 35566 2685 60 44 5280 M9K auto 1410.8 MiB 217.85 527418 1961355 698273 1211201 51881 2014.4 MiB 213.62 1.87 11.5444 -297926 -10.5444 7.43875 0.09 0.221174 0.167818 25.4392 19.6023 799544 22.4850 206009 5.79344 140764 494647 491987729 117958703 0 0 1.08858e+08 20617.0 42 1675578 19868374 -1 14.3661 7.89936 -391318 -13.3661 0 0 40.95 -1 -1 2014.4 MiB 168.06 45.7164 36.8171 2014.4 MiB -1 248.05 +3d_SB_inter_die_stratixiv_arch.timing.xml EKF-SLAM_Jacobians_stratixiv_arch_timing.blif common 1128.29 vpr 1.92 GiB 574 2772 16 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2014856 4 570 66175 54803 2 39317 3362 51 38 3876 LAB auto 1449.1 MiB 197.04 539555 2646737 936545 1618816 91376 1861.6 MiB 263.14 2.12 27.205 -106349 -26.205 5.36288 0.06 0.222737 0.17179 26.4811 20.5787 812545 20.6691 203996 5.18915 179839 704950 1238086925 342084780 0 0 7.97022e+07 20563.0 22 1225854 14507865 -1 30.7692 6.31053 -122652 -29.7692 0 0 28.44 -1 -1 1865.0 MiB 437.18 39.1867 31.6218 1861.6 MiB -1 162.84 +3d_SB_inter_die_stratixiv_arch.timing.xml fir_cascade_stratixiv_arch_timing.blif common 2111.69 vpr 4.79 GiB 40 3678 172 1 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 5023412 19 21 171111 96274 1 73063 3891 129 96 24768 DSP auto 1882.4 MiB 124.10 683749 3705402 1474779 2203663 26960 4905.7 MiB 149.84 1.99 4.90769 -102144 -3.90769 2.66229 0.32 0.333623 0.299825 45.1483 39.2326 943364 12.9122 246384 3.37235 150431 182369 732288583 298849219 0 0 5.14406e+08 20769.0 11 7758968 93673935 -1 5.35185 3.87959 -147181 -4.35185 0 0 181.00 -1 -1 4905.7 MiB 286.71 59.0156 52.1235 4905.7 MiB -1 1092.75 +3d_SB_inter_die_stratixiv_arch.timing.xml jacobi_stratixiv_arch_timing.blif common 564.65 vpr 1.64 GiB 536 1953 7 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1718716 227 309 49176 40422 1 28164 2500 47 35 3290 io auto 1277.5 MiB 145.88 261565 1868100 672501 1151002 44597 1646.7 MiB 140.05 1.34 195.231 -110925 -194.231 195.231 0.06 0.12554 0.0992061 14.6571 11.6553 411249 14.6040 113307 4.02369 103543 325921 298122992 61172575 0 0 6.75216e+07 20523.3 20 1033138 12274942 -1 199.286 199.286 -155282 -198.286 0 0 25.18 -1 -1 1646.7 MiB 79.16 22.1044 18.1436 1646.7 MiB -1 142.30 +3d_SB_inter_die_stratixiv_arch.timing.xml JPEG_stratixiv_arch_timing.blif common 695.10 vpr 1.80 GiB 36 1342 8 149 2 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1888536 3 33 52402 39411 1 28062 1537 57 42 4788 M9K auto 1243.2 MiB 103.70 273438 790611 224541 541418 24652 1844.3 MiB 92.12 0.90 15.273 -287167 -14.273 15.273 0.08 0.114449 0.0977109 12.57 10.0601 460533 16.4159 127882 4.55842 95816 245821 618088152 166535403 0 0 9.85096e+07 20574.3 47 1507654 17957159 -1 17.7356 17.7356 -355280 -16.7356 0 0 36.56 -1 -1 1844.3 MiB 212.41 25.6811 21.3256 1844.3 MiB -1 217.95 +3d_SB_inter_die_stratixiv_arch.timing.xml leon2_stratixiv_arch_timing.blif common 201.82 vpr 1.28 GiB 251 954 1 17 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1341092 55 196 20131 19956 1 8282 1223 32 24 1536 LAB auto 1088.4 MiB 65.74 108189 537257 161186 351024 25047 1309.7 MiB 24.49 0.28 7.63348 -66340.6 -6.63348 7.63348 0.02 0.0446494 0.0376164 4.56397 3.53477 173240 20.9252 49009 5.91968 28613 116746 69432612 13114190 0 0 3.14199e+07 20455.7 16 483264 5705245 -1 8.73313 8.73313 -81669.2 -7.73313 0 0 11.99 -1 -1 1309.7 MiB 20.35 7.28084 5.9123 1309.7 MiB -1 59.04 +3d_SB_inter_die_stratixiv_arch.timing.xml leon3mp_stratixiv_arch_timing.blif common 574.17 vpr 1.54 GiB 255 2123 1 28 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1610160 84 171 36458 36247 3 20352 2407 45 33 2970 LAB auto 1230.9 MiB 176.26 230253 1534187 537107 918935 78145 1542.6 MiB 80.31 0.73 10.3286 -73217.5 -9.32864 4.15911 0.04 0.109206 0.091457 12.2567 9.37699 386386 18.9982 105938 5.20887 59158 205458 343044614 94954046 0 0 6.09438e+07 20519.8 15 935204 11078823 -1 11.9822 4.48722 -86968.8 -10.9822 0 0 22.88 -1 -1 1542.6 MiB 135.83 18.0758 14.384 1542.6 MiB -1 130.74 +3d_SB_inter_die_stratixiv_arch.timing.xml MCML_stratixiv_arch_timing.blif common 895.60 vpr 2.42 GiB 69 2107 10 295 16 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2536012 36 33 57796 49182 1 20334 2497 79 59 9322 M144K auto 1353.6 MiB 114.46 211332 2152988 849915 1253916 49157 2476.6 MiB 97.43 0.82 9.56163 -84792.3 -8.56163 9.56163 0.14 0.126043 0.0984021 17.6076 13.911 393751 19.3689 103359 5.08431 69197 220461 288511556 81052098 0 0 1.92002e+08 20596.6 45 2917968 35039980 -1 9.93304 9.93304 -167341 -8.93304 0 0 69.52 -1 -1 2476.6 MiB 110.65 31.348 25.8958 2476.6 MiB -1 452.70 +3d_SB_inter_die_stratixiv_arch.timing.xml MMM_stratixiv_arch_timing.blif common 733.35 vpr 2.14 GiB 478 1231 1 300 4 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2246596 202 276 35125 30509 3 21728 2014 73 54 7884 M9K auto 1186.1 MiB 98.22 226155 1680130 581037 1021138 77955 2193.9 MiB 81.38 0.58 9.04734 -32184.9 -8.04734 3.17119 0.12 0.12349 0.0925998 16.6945 12.9764 376551 17.3350 90231 4.15390 60533 167938 291951174 74695878 0 0 1.62738e+08 20641.5 20 2479452 29744051 -1 9.34711 3.98413 -48329.1 -8.34711 0 0 58.73 -1 -1 2193.9 MiB 97.89 23.8118 19.2322 2193.9 MiB -1 359.25 +3d_SB_inter_die_stratixiv_arch.timing.xml radar20_stratixiv_arch_timing.blif common 303.46 vpr 1.46 GiB 5 330 31 105 0 2 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1536028 3 2 14862 10304 26 7620 473 49 36 3528 DSP auto 1035.1 MiB 49.34 86372 144149 35218 93920 15011 1500.0 MiB 9.09 0.10 5.35635 -20850.9 -4.35635 3.73741 0.06 0.0454616 0.0396929 4.33095 3.6643 150545 19.8242 37129 4.88925 20992 47091 119548029 36655524 0 0 7.26079e+07 20580.5 20 1120110 13214470 -1 5.84657 3.77061 -40487 -4.84657 0 0 26.93 -1 -1 1500.0 MiB 45.25 7.43604 6.47906 1500.0 MiB -1 151.75 +3d_SB_inter_die_stratixiv_arch.timing.xml random_stratixiv_arch_timing.blif common 585.18 vpr 1.82 GiB 693 1777 25 16 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1904188 35 658 51416 37539 1 27463 2511 58 43 4988 io auto 1277.9 MiB 98.57 206877 1998531 678358 1182926 137247 1859.6 MiB 115.66 0.95 40.5043 -60922.5 -39.5043 40.5043 0.09 0.122326 0.107203 16.9254 13.7612 342117 13.1822 91004 3.50649 77091 229186 193704618 53247878 0 0 1.02587e+08 20566.7 33 1568252 18700371 -1 39.0491 39.0491 -68044.3 -38.0491 0 0 37.83 -1 -1 1859.6 MiB 69.44 28.0298 23.4918 1859.6 MiB -1 227.84 +3d_SB_inter_die_stratixiv_arch.timing.xml Reed_Solomon_stratixiv_arch_timing.blif common 484.44 vpr 1.83 GiB 753 1108 5 32 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1915040 13 740 25173 25306 1 12781 1898 63 47 5922 io auto 1130.4 MiB 72.36 122373 1223482 442946 725936 54600 1870.2 MiB 43.47 0.37 8.58151 -26013.6 -7.58151 8.58151 0.09 0.066611 0.0577751 8.09623 6.55743 181674 14.2222 45570 3.56740 33303 126130 60438024 14474337 0 0 1.22008e+08 20602.6 22 1871156 22275272 -1 9.64216 8.37594 -35791.4 -8.64216 0 0 44.59 -1 -1 1870.2 MiB 22.83 12.7955 10.6758 1870.2 MiB -1 273.45 +3d_SB_inter_die_stratixiv_arch.timing.xml smithwaterman_stratixiv_arch_timing.blif common 623.34 vpr 1.70 GiB 117 2173 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1781144 79 38 66795 54922 1 36442 2290 46 34 3128 LAB auto 1333.0 MiB 118.38 223063 1496002 445875 1009592 40535 1631.3 MiB 130.59 1.12 10.298 -164963 -9.29802 10.298 0.05 0.147236 0.114284 15.8825 12.406 335721 9.21323 96583 2.65054 148171 339963 462293429 109838402 0 0 6.41689e+07 20514.4 61 983570 11662836 -1 11.0507 11.0507 -199170 -10.0507 0 0 24.26 -1 -1 1656.6 MiB 176.26 36.1483 29.4745 1631.3 MiB -1 139.48 +3d_SB_inter_die_stratixiv_arch.timing.xml stap_steering_stratixiv_arch_timing.blif common 434.07 vpr 1.65 GiB 213 1565 26 4 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1733820 139 74 57121 41054 1 24175 1808 49 36 3528 DSP auto 1291.2 MiB 90.16 142328 1212908 383501 795665 33742 1665.9 MiB 78.06 0.70 5.18054 -15486.2 -4.18054 4.55771 0.06 0.122967 0.105902 15.1532 12.538 255792 10.5826 76054 3.14650 55778 101786 129669669 38217209 0 0 7.26079e+07 20580.5 17 1120110 13214470 -1 5.89185 5.89185 -31809.1 -4.89185 0 0 27.24 -1 -1 1665.9 MiB 49.95 22.1936 18.8747 1665.9 MiB -1 159.11 +3d_SB_inter_die_stratixiv_arch.timing.xml sudoku_check_stratixiv_arch_timing.blif common 203.83 vpr 1.26 GiB 54 659 0 40 0 1 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1324232 2 52 16673 16662 2 12066 754 32 24 1536 M9K auto 1066.4 MiB 53.90 155566 261434 69464 171581 20389 1293.2 MiB 20.41 0.23 5.61272 -16670 -4.61272 4.76097 0.02 0.058552 0.0457308 5.08816 4.03513 232798 19.3001 64048 5.30990 55982 170058 137168149 27075994 0 0 3.14199e+07 20455.7 17 483264 5705245 -1 6.79545 5.55783 -24965 -5.79545 0 0 12.04 -1 -1 1293.2 MiB 38.89 8.66706 7.15564 1293.2 MiB -1 59.00 +3d_SB_inter_die_stratixiv_arch.timing.xml SURF_desc_stratixiv_arch_timing.blif common 605.13 vpr 1.77 GiB 445 2151 19 52 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1857416 131 314 57881 45152 1 32955 2667 49 36 3528 DSP auto 1362.9 MiB 121.73 289015 2017750 707990 1212909 96851 1716.4 MiB 185.57 1.75 193.424 -63656.5 -192.424 193.424 0.05 0.181205 0.144741 21.1471 16.9918 454441 13.8208 122774 3.73389 118181 360293 262822432 52549899 0 0 7.26079e+07 20580.5 21 1120110 13214470 -1 194.404 194.404 -85184.9 -193.404 0 0 27.34 -1 -1 1734.0 MiB 79.07 32.7617 27.124 1716.4 MiB -1 156.20 +3d_SB_inter_die_stratixiv_arch.timing.xml ucsb_152_tap_fir_stratixiv_arch_timing.blif common 99.58 vpr 1.19 GiB 42 752 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1244496 13 29 26295 20086 1 12509 794 29 21 1218 LAB auto 1062.7 MiB 15.63 61236 243344 47038 181714 14592 1215.3 MiB 10.40 0.15 5.00346 -4267.82 -4.00346 2.38962 0.02 0.0231436 0.0188542 1.7862 1.47025 95550 7.63972 32943 2.63397 28913 41935 41958000 8761950 0 0 2.48366e+07 20391.3 15 382818 4502703 -1 5.19398 2.70192 -5808.39 -4.19397 0 0 9.42 -1 -1 1215.3 MiB 11.07 3.16143 2.70178 1215.3 MiB -1 33.35 +3d_SB_inter_die_stratixiv_arch.timing.xml uoft_raytracer_stratixiv_arch_timing.blif common 909.95 vpr 2.27 GiB 964 977 19 34 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2381096 542 422 37277 26038 1 20599 1994 78 58 9048 io auto 1149.6 MiB 67.08 196066 1482304 530853 872654 78797 2325.3 MiB 124.70 1.43 7.36978 -33273.5 -6.36978 7.36978 0.13 0.0925632 0.0749752 12.0148 9.72001 324180 15.7399 87235 4.23553 91508 211619 398061242 137241372 0 0 1.86852e+08 20651.1 51 2837414 34147767 -1 8.24329 7.76567 -42592.4 -7.24329 0 0 66.15 -1 -1 2325.3 MiB 174.89 22.8404 19.2662 2325.3 MiB -1 437.08 +3d_SB_inter_die_stratixiv_arch.timing.xml wb_conmax_stratixiv_arch_timing.blif common 828.65 vpr 2.52 GiB 1107 729 0 0 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 2643872 403 704 15490 16194 1 8574 1836 88 65 11440 io auto 1060.4 MiB 54.12 128760 1372872 549171 784185 39516 2581.9 MiB 33.58 0.32 10.7454 -16424.4 -9.74539 5.1543 0.17 0.0471481 0.041409 6.67367 5.49523 170198 19.8528 38778 4.52327 24095 94572 111221252 37508416 0 0 2.36204e+08 20647.2 15 3590540 43137666 -1 12.3144 5.56074 -24951.7 -11.3144 0 0 82.34 -1 -1 2581.9 MiB 53.56 9.31536 7.88036 2581.9 MiB -1 555.23 +3d_SB_inter_die_stratixiv_arch.timing.xml picosoc_stratixiv_arch_timing.blif common 160.17 vpr 1.18 GiB 35 730 0 6 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1239888 18 17 16969 16357 1 6277 771 28 21 1176 LAB auto 1057.4 MiB 68.96 72908 258753 67776 184461 6516 1210.8 MiB 13.14 0.19 7.51407 -40222.8 -6.51407 7.51407 0.02 0.031379 0.0262939 2.92773 2.28009 115032 18.3376 32494 5.17998 21478 112529 39563291 7329073 0 0 2.39639e+07 20377.5 45 369794 4343188 -1 8.81565 8.81565 -49666.3 -7.81565 0 0 9.04 -1 -1 1210.8 MiB 13.32 6.56727 5.39667 1210.8 MiB -1 35.56 +3d_SB_inter_die_stratixiv_arch.timing.xml murax_stratixiv_arch_timing.blif common 29.27 vpr 993.75 MiB 35 73 0 8 0 0 success v8.0.0-11651-ge18409e-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-142-generic x86_64 2024-10-31T16:58:00 agent-3 /home/mohagh18/vtr-verilog-to-routing/vtr_flow/tasks 1017596 18 17 2291 2142 1 1500 116 13 10 260 LAB auto 953.5 MiB 7.20 9940 8576 1032 6562 982 993.7 MiB 0.50 0.01 5.31743 -3552.51 -4.31743 4.26751 0.00 0.00438277 0.00337059 0.190292 0.160703 16521 11.0361 5707 3.81229 4108 9384 4537270 913138 0 0 4.97530e+06 19135.8 34 75766 878809 -1 5.39567 4.83189 -4585.23 -4.39567 0 0 2.12 -1 -1 993.7 MiB 1.43 0.596507 0.52271 993.7 MiB -1 2.56 diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt index 47c2eba43f0..ab09aacaf5a 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/task_list.txt @@ -3,5 +3,7 @@ regression_tests/vtr_reg_nightly_test7/titan_other_run_flat #regression_tests/vtr_reg_nightly_test7/vtr_reg_qor_large_depop_run_flat #regression_tests/vtr_reg_nightly_test7/verify_router_lookahead_run_flat regression_tests/vtr_reg_nightly_test7/verify_rr_graph_run_flat -regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_auto_bb -regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb +regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_auto_bb +regression_tests/vtr_reg_nightly_test7/3d_cb_titan_other_cube_bb +regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_auto_bb +regression_tests/vtr_reg_nightly_test7/3d_sb_titan_other_per_layer_bb