Settle on an x64 register order

[ltratt]

DWARF and pretty much everyone else use different indices for x64 register numbers. From our perspective, the DWARF source of truth is ykllvm's X86RegisterInfo.td file. From that we can derive the orderings::

Index	DWARF	Everyone else
0	RAX	RAX
1	RDX	RCX
2	RCX	RDX
3	RBX	RBX
4	RSI	RSP
5	RDI	RBP
6	RBP	RSI
7	RSP	RDI
8	R8	R8
9	R9	R9
10	R10	R10
11	R11	R11
12	R12	R12
13	R13	R13
14	R14	R14
15	R15	R15
16	RIP	RIP

If I live to be 1000 I will not understand why this happened, how, or... well, you get the idea.

Unfortunately, we have chosen the worst of all worlds: we use both orderings and interleave them all over the shop. This leads to significant complexity and -- worse! -- confusion. I've just spent half an hour hunting down seeming weirdness that's just an artefact of us using both schemes.

We should settle on one of these schemes and use it consistently. It seems to me the only sensible scheme is the not-DWARF scheme. That means that yksmp should translate the DWARF numbers to the non-DWARF scheme, and then in ykrt we will only have to deal with the normal (non-DWARF) register numbers!

[vext01]

For what it's worth, here are the 64-bit register numbers in the AMD manual:

And here they are in the intel manual (r8-15 not shown here):

I was curious as to why the schemes differ. I asked an AI and it reckons it because DWARF numbers registers according to their use in the ABI, not according to any given architecture. I guess what it means by this is that in DWARF (e.g.) the stack pointer is always 7 regardless of the CPU architecture.

[ltratt]

Yes, those are the same as the "everyone else" column (slightly obscured by their odd indexing on the LHS of the screengrab, which is non-monotonic).