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11 Open 9 Closed
11 Open 9 Closed
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Issues list

0x00 and 0xFF give IndexOutOfBounds errors
#20 opened Nov 13, 2014 by bder
two compiler warnings
#18 opened Jul 31, 2014 by bder
0x16 precompute gives 10 gates instead of 9. bug
#17 opened Jul 23, 2014 by bder
Check espresso
#16 opened Jul 22, 2014 by PrashantVaidyanathan NetSynth Tests
check abc
#15 opened Jul 22, 2014 by PrashantVaidyanathan NetSynth Tests
Check double inverters
#14 opened Jul 22, 2014 by PrashantVaidyanathan NetSynth Tests
Test 2 nots to nor
#13 opened Jul 22, 2014 by PrashantVaidyanathan NetSynth Tests
Create a test function for all n input circuits and verify correctness
#12 opened Jul 22, 2014 by PrashantVaidyanathan NetSynth Tests
for precompute synthesis, a dangling OUTPUT gate exists name WireX
#10 opened Jul 22, 2014 by bder
Change runABC to accept filepath instead of file name (esp for Blif files) enhancement
#6 opened May 7, 2014 by PrashantVaidyanathan
@PrashantVaidyanathan
Parse Structural Verilog to Netlist has issues with multiple outputs. bug
#5 opened Apr 28, 2014 by PrashantVaidyanathan
@PrashantVaidyanathan
5
ProTip! Updated in the last three days: updated:>2025-02-01.