Add a "xcheri-std-compat" mode to LLVM

clang/include/clang/Driver/Options.td

@@ -3919,6 +3919,14 @@ def mno_xcheri_v9_semantics : Flag<["-"], "mno-xcheri-v9-semantics">, Group<m_ri
 // Add an alias with a more sensible name for when the default is flipped.
 def mxcheri_v8_compat : Flag<["-"], "mxcheri-v8-compat">, Alias<mno_xcheri_v9_semantics>;
 
+def mxcheri_std_compat : Flag<["-"], "mxcheri-std-compat">,
+                         Group<m_riscv_Features_Group>,
+                         HelpText<"Enable the subset of CHERI features that "
+                                  "are compatible with the upcoming standard">;
+def mno_xcheri_std_compat : Flag<["-"], "mno-xcheri-std-compat">,
+                            Group<m_riscv_Features_Group>,
+                            HelpText<"Enable non-standard CHERI features">;
+
 def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>,
   HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64/LoongArch only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_Group>,

clang/lib/Basic/Targets/RISCV.cpp

@@ -177,8 +177,11 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
     auto ExtName = Extension.first;
     auto ExtInfo = Extension.second;
 
+    // Replace '-' with '_' to ensure the result is a single PP token.
+    std::string EscapedName = ExtName;
+    std::replace(EscapedName.begin(), EscapedName.end(), '-', '_');
     Builder.defineMacro(
-        Twine("__riscv_", ExtName),
+        Twine("__riscv_", EscapedName),
         Twine(getVersionValue(ExtInfo.MajorVersion, ExtInfo.MinorVersion)));
   }
 
@@ -348,7 +351,6 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
                     .Case("riscv64", Is64Bit)
                     .Case("32bit", !Is64Bit)
                     .Case("64bit", Is64Bit)
-                    .Case("xcheri", HasCheri)
                     .Default(std::nullopt);
   if (Result)
     return *Result;

clang/lib/Driver/ToolChains/Arch/RISCV.cpp

@@ -179,18 +179,6 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
     Features.push_back("-relax");
   }
 
-  if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
-    bool IsPureCapability = isCheriPurecapABIName(A->getValue());
-    if (IsPureCapability) {
-      if (llvm::find(Features, "+xcheri") == Features.end()) {
-        D.Diag(diag::err_riscv_invalid_abi) << A->getValue()
-          << "pure capability ABI requires xcheri extension to be specified";
-        return;
-      }
-      Features.push_back("+cap-mode");
-    }
-  }
-
   // GCC Compatibility: -mno-save-restore is default, unless -msave-restore is
   // specified.
   if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore, false))
@@ -202,6 +190,26 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   // which may override the defaults.
   handleTargetFeaturesGroup(D, Triple, Args, Features,
                             options::OPT_m_riscv_Features_Group);
+
+  if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
+    bool IsPureCapability = isCheriPurecapABIName(A->getValue());
+    if (IsPureCapability) {
+      auto ISAInfo = llvm::RISCVISAInfo::parseFeatures(
+          Triple.isArch32Bit() ? 32 : 64,
+          std::vector<std::string>(Features.begin(), Features.end()));
+      if (!ISAInfo) {
+        handleAllErrors(ISAInfo.takeError(), [&](llvm::StringError &ErrMsg) {
+          D.Diag(diag::err_invalid_feature_combination) << ErrMsg.getMessage();
+        });
+      } else if (!(*ISAInfo)->hasExtension("xcheri")) {
+        D.Diag(diag::err_riscv_invalid_abi)
+            << A->getValue()
+            << "pure capability ABI requires xcheri extension to be specified";
+        return;
+      }
+      Features.push_back("+cap-mode");
+    }
+  }
 }
 
 StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {

clang/lib/Headers/cheri_init_globals.h

@@ -76,13 +76,13 @@ __attribute__((weak)) extern void *__capability __cap_table_end;
  * position-dependent executables.
  */
 #ifdef CHERI_INIT_GLOBALS_USE_OFFSET
-#define cgetaddr_or_offset "cgetoffset"
 #define csetaddr_or_offset "csetoffset"
+#define cheri_address_or_offset_get(_cap) __builtin_cheri_offset_get((_cap))
 #define cheri_address_or_offset_set(_cap, _val)                                \
   __builtin_cheri_offset_set((_cap), (_val))
 #else
-#define cgetaddr_or_offset "cgetaddr"
 #define csetaddr_or_offset "csetaddr"
+#define cheri_address_or_offset_get(_cap) __builtin_cheri_address_get((_cap))
 #define cheri_address_or_offset_set(_cap, _val)                                \
   __builtin_cheri_address_set((_cap), (_val))
 #endif
@@ -219,13 +219,11 @@ cheri_init_globals_3(void *__capability data_cap,
           "lla %1, __stop___cap_relocs\n\t"
           : "=r"(start_addr), "=r"(stop_addr));
 #else
-  void *__capability tmp;
-  __asm__ (
-       "cllc %2, __start___cap_relocs\n\t"
-       cgetaddr_or_offset " %0, %2\n\t"
-       "cllc %2, __stop___cap_relocs\n\t"
-       cgetaddr_or_offset " %1, %2\n\t"
-       :"=r"(start_addr), "=r"(stop_addr), "=&C"(tmp));
+  __asm__("cllc %0, __start___cap_relocs\n\t"
+          "cllc %1, __stop___cap_relocs\n\t"
+          : "=C"(start_relocs), "=C"(stop_relocs));
+  start_addr = cheri_address_or_offset_get(start_relocs);
+  stop_addr = cheri_address_or_offset_get(stop_relocs);
 #endif
 #else
 #error Unknown architecture

clang/lib/Sema/SemaChecking.cpp

@@ -236,6 +236,18 @@ static bool SemaBuiltinCHERICapCreate(Sema &S, CallExpr *TheCall) {
   return false;
 }
 
+/// Check whether we are targeting the RISC-V CHERI standard, and if we are emit
+/// an appropriate error message
+static bool checkNonStdCheriIntrin(Sema &S, CallExpr *TheCall) {
+  const auto &TI = S.Context.getTargetInfo();
+  if (TI.getTriple().isRISCV() && TI.hasFeature("xcheri-std-compat")) {
+    S.Diag(TheCall->getBeginLoc(), diag::err_riscv_builtin_requires_extension)
+        << true << TheCall->getSourceRange() << "xcheri (without std-compat)";
+    return true;
+  }
+  return false;
+}
+
 /// Check that argument \p ArgIndex is a capability type (or an array/function
 /// that decays to a capability type.
 static bool checkCapArg(Sema &S, CallExpr *TheCall, unsigned ArgIndex,
@@ -2639,10 +2651,16 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID,
     }
     break;
   }
+  case Builtin::BI__builtin_cheri_cap_load_tags:
+    if (checkNonStdCheriIntrin(*this, TheCall))
+      return ExprError(); // Not supported in standard CHERI RISC-V
+    break;
   case Builtin::BI__builtin_cheri_seal:
   case Builtin::BI__builtin_cheri_unseal:
   case Builtin::BI__builtin_cheri_conditional_seal:
   case Builtin::BI__builtin_cheri_cap_type_copy: {
+    if (checkNonStdCheriIntrin(*this, TheCall))
+      return ExprError(); // Not supported in standard CHERI RISC-V
     // Seal/unseal work in almost same way as the setters: value to be
     // unsealed/sealed comes first and should therefore be the result type,
     // second argument is overloaded to be any capability type.

clang/test/Driver/riscv-default-features.c

@@ -16,6 +16,16 @@
 // RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -mxcheri-v9-semantics -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-V9
 // RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -mxcheri-v8-compat -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-V8
 
+/// The standards-compatible mode can be enable either using the arch string or the -mxcheri-std-compat flag
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -mxcheri-std-compat -S -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=RV64-XCHERI-STD-COMPAT
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri_xcheri-std-compat -S -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=RV64-XCHERI-STD-COMPAT
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri-std-compat -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-STD-COMPAT
+/// In the case of rv64i -mxcheri-std-compat, +xcheri is not inferred, but this will be fixed in future upstream merges
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64i -mxcheri-std-compat -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI-STD-COMPAT-ONLY
+/// Check that we can override the flag with -mno-xcheri-std-compat
+// RUN: %clang --target=riscv64-unknown-elf -march=rv64ixcheri -mxcheri-std-compat -mno-xcheri-std-compat -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64-XCHERI
+
+
 // RV32: "target-features"="+32bit,+a,+c,+m,+relax,
 // RV32-SAME: -save-restore
 // RV64: "target-features"="+64bit,+a,+c,+m,+relax,
@@ -48,6 +58,9 @@
 // RV64-XCHERI-V9-SAME: +xcheri-v9-semantics
 // RV64-XCHERI-V9-SAME: -save-restore
 
+// RV64-XCHERI-STD-COMPAT: "target-features"="+64bit,+relax,+xcheri,+xcheri-std-compat,
+// RV64-XCHERI-STD-COMPAT-ONLY: "target-features"="+64bit,+relax,+xcheri-std-compat,
+
 // Dummy function
 int foo(void){
   return  3;

clang/test/Driver/riscv-features.c

@@ -32,6 +32,7 @@
 // RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv64ixcheri -mxcheri-norvc 2>&1 | FileCheck %s --check-prefixes=XCHERI,XCHERI-NORVC
 // RUN: %clang --target=riscv32-unknown-elf -### %s -march=rv64ixcheri -mno-xcheri-rvc 2>&1 | FileCheck %s --check-prefixes=XCHERI,XCHERI-NORVC
 // XCHERI: "-target-feature" "+xcheri"
+// XCHERI: "-xcheri-std-compat"
 // XCHERI-NOT: "{{[+|-]}}xcheri-
 // XCHERI-EXPLICIT-RVC: "-target-feature" "-xcheri-norvc"
 // XCHERI-NORVC: "-target-feature" "+xcheri-norvc"

clang/test/Preprocessor/riscv-target-features.c

@@ -780,3 +780,37 @@
 // RUN: -march=rv64i_zacas1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
 // CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
+
+// RUN: %clang -target riscv64-unknown-none -march=rv64gcxcheri -x c -E -dM %s \
+// RUN:   -o - | FileCheck %s --check-prefixes=CHECK-XCHERI --implicit-check-not=__riscv_
+// RUN: %clang -target riscv64-unknown-none -march=rv64gcxcheri -mxcheri-std-compat -x c -E -dM %s \
+// RUN:   -o - | FileCheck %s --check-prefixes=CHECK-XCHERI,CHECK-XCHERI-STD-COMPAT --implicit-check-not=__riscv_
+
+
+// CHECK-XCHERI:      #define __riscv 1
+// CHECK-XCHERI-NEXT: #define __riscv_a 2001000
+// CHECK-XCHERI-NEXT: #define __riscv_arch_test 1
+// CHECK-XCHERI-NEXT: #define __riscv_atomic 1
+// CHECK-XCHERI-NEXT: #define __riscv_c 2000000
+// CHECK-XCHERI-NEXT: #define __riscv_clen 128
+// CHECK-XCHERI-NEXT: #define __riscv_cmodel_medlow 1
+// CHECK-XCHERI-NEXT: #define __riscv_compressed 1
+// CHECK-XCHERI-NEXT: #define __riscv_d 2002000
+// CHECK-XCHERI-NEXT: #define __riscv_div 1
+// CHECK-XCHERI-NEXT: #define __riscv_f 2002000
+// CHECK-XCHERI-NEXT: #define __riscv_fdiv 1
+// CHECK-XCHERI-NEXT: #define __riscv_flen 64
+// CHECK-XCHERI-NEXT: #define __riscv_float_abi_double 1
+// CHECK-XCHERI-NEXT: #define __riscv_fsqrt 1
+// CHECK-XCHERI-NEXT: #define __riscv_i 2001000
+// CHECK-XCHERI-NEXT: #define __riscv_m 2000000
+// CHECK-XCHERI-NEXT: #define __riscv_mul 1
+// CHECK-XCHERI-NEXT: #define __riscv_muldiv 1
+// CHECK-XCHERI-NEXT: #define __riscv_xcheri 0
+// CHECK-XCHERI-NEXT: #define __riscv_xcheri_mode_dependent_jumps 1
+// CHECK-XCHERI-STD-COMPAT-NEXT: #define __riscv_xcheri_std_compat 0
+// CHECK-XCHERI-NEXT: #define __riscv_xlen 64
+// CHECK-XCHERI-NEXT: #define __riscv_zicsr 2000000
+// CHECK-XCHERI-NEXT: #define __riscv_zifencei 2000000
+
+

clang/test/Sema/cheri/cheri-std-unsupported-builtins.c

@@ -0,0 +1,25 @@
+/// In the RISC-V standard compat mode not all builtins are supported since we do not perform the expansion in the backend.
+// RUN: %riscv64_cheri_purecap_cc1 -target-feature +xcheri %s -fsyntax-only -verify=xcheri
+// RUN: %riscv64_cheri_purecap_cc1 -target-feature +xcheri-std-compat %s -fsyntax-only -verify=std-compat
+// xcheri-no-diagnostics
+
+void *cseal(void *a, void *b) {
+  _Static_assert(__has_builtin(__builtin_cheri_seal), ""); // TODO: would be nice to report false here
+  return __builtin_cheri_seal(a, b); // std-compat-error{{builtin requires at least one of the following extensions to be enabled: xcheri (without std-compat)}}
+}
+void *cunseal(void *a, void *b) {
+  _Static_assert(__has_builtin(__builtin_cheri_unseal), ""); // TODO: would be nice to report false here
+  return __builtin_cheri_unseal(a, b); // std-compat-error{{builtin requires at least one of the following extensions to be enabled: xcheri (without std-compat)}}
+}
+void *ccseal(void *a, void *b) {
+  _Static_assert(__has_builtin(__builtin_cheri_conditional_seal), ""); // TODO: would be nice to report false here
+  return __builtin_cheri_conditional_seal(a, b); // std-compat-error{{builtin requires at least one of the following extensions to be enabled: xcheri (without std-compat)}}
+}
+void *ccopytype(void *a, void *b) {
+  _Static_assert(__has_builtin(__builtin_cheri_cap_type_copy), ""); // TODO: would be nice to report false here
+  return __builtin_cheri_cap_type_copy(a, b); // std-compat-error{{builtin requires at least one of the following extensions to be enabled: xcheri (without std-compat)}}
+}
+unsigned long cloadtags(void *a) {
+  _Static_assert(__has_builtin(__builtin_cheri_cap_load_tags), ""); // TODO: would be nice to report false here
+  return __builtin_cheri_cap_load_tags(a); // std-compat-error{{builtin requires at least one of the following extensions to be enabled: xcheri (without std-compat)}}
+}

llvm/include/llvm/CodeGen/TargetLowering.h

@@ -3258,6 +3258,7 @@ class TargetLoweringBase {
 
   // Return true if the target has a capability set address instruction.
   virtual bool hasCapabilitySetAddress() const { return false; }
+  virtual bool hasCapabilitySetOffset() const { return true; }
   MVT cheriCapabilityType() const { return CapType; }
   bool cheriCapabilityTypeHasPreciseBounds() const {
     return CapTypeHasPreciseBounds;

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -7488,6 +7488,33 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
     setValue(&I, Res);
     return;
   }
+  case Intrinsic::cheri_cap_offset_set: {
+    if (TLI.hasCapabilitySetOffset()) {
+      visitTargetIntrinsic(I, Intrinsic);
+      return;
+    }
+    assert(TLI.hasCapabilitySetAddress() &&
+           "Expansion of offset_set requires address_set!");
+    Value *CapV = I.getArgOperand(0);
+    SDValue Cap = getValue(CapV);
+    Value *OffsetV = I.getArgOperand(1);
+    SDValue Offset = getValue(OffsetV);
+    // offset_set(cap, offset) -> address_set(cap, base_get(cap) + offset)
+    EVT AddrVT = TLI.getPointerRangeTy(
+        DAG.getDataLayout(), CapV->getType()->getPointerAddressSpace());
+    EVT CapVT = TLI.getPointerTy(DAG.getDataLayout(),
+                                 CapV->getType()->getPointerAddressSpace());
+    SDValue CapBase = DAG.getNode(
+        ISD::INTRINSIC_WO_CHAIN, sdl, AddrVT,
+        DAG.getConstant(Intrinsic::cheri_cap_base_get, sdl, AddrVT), Cap);
+    SDValue NewAddr = DAG.getNode(ISD::ADD, sdl, AddrVT, CapBase, Offset);
+    Res = DAG.getNode(
+        ISD::INTRINSIC_WO_CHAIN, sdl, CapVT,
+        DAG.getConstant(Intrinsic::cheri_cap_address_set, sdl, AddrVT), Cap,
+        NewAddr);
+    setValue(&I, Res);
+    return;
+  }
   case Intrinsic::threadlocal_address: {
     setValue(&I, getValue(I.getOperand(0)));
     return;

llvm/lib/Support/RISCVISAInfo.cpp

@@ -68,6 +68,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
 
     // vendor-defined ('X') extensions
     {"xcheri", RISCVExtensionVersion{0, 0}},
+    {"xcheri-std-compat", RISCVExtensionVersion{0, 0}},
     {"xcvbitmanip", RISCVExtensionVersion{1, 0}},
     {"xcvmac", RISCVExtensionVersion{1, 0}},
     {"xsfcie", RISCVExtensionVersion{1, 0}},
@@ -955,6 +956,7 @@ Error RISCVISAInfo::checkDependency() {
 static const char *ImpliedExtsD[] = {"f"};
 static const char *ImpliedExtsF[] = {"zicsr"};
 static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
+static const char *ImpliedExtsXCheriStdCompat[] = {"xcheri"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
 static const char *ImpliedExtsZacas[] = {"a"};
@@ -1021,6 +1023,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"d"}, {ImpliedExtsD}},
     {{"f"}, {ImpliedExtsF}},
     {{"v"}, {ImpliedExtsV}},
+    {{"xcheri-std-compat"}, {ImpliedExtsXCheriStdCompat}},
     {{"xsfvcp"}, {ImpliedExtsXsfvcp}},
     {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
     {{"zacas"}, {ImpliedExtsZacas}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

@@ -119,7 +119,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
   ParseStatus parseDirective(AsmToken DirectiveID) override;
 
   bool isCheri() const override {
-    return getSTI().getFeatureBits()[RISCV::FeatureCheri];
+    return getSTI().getFeatureBits()[RISCV::FeatureCheriCommon];
   }
 
   unsigned getCheriCapabilitySize() const override {
@@ -3064,7 +3064,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
     if (Parser.parseEOL())
       return true;
 
-    if (!getSTI().hasFeature(RISCV::FeatureCheri))
+    if (!getSTI().hasFeature(RISCV::FeatureXCheri))
       return Error(Parser.getTok().getLoc(),
                    "option requires 'xcheri' extension");
 
@@ -3077,7 +3077,7 @@ bool RISCVAsmParser::parseDirectiveOption() {
     if (Parser.parseEOL())
       return true;
 
-    if (!getSTI().hasFeature(RISCV::FeatureCheri))
+    if (!getSTI().hasFeature(RISCV::FeatureXCheri))
       return Error(Parser.getTok().getLoc(),
                    "option requires 'xcheri' extension");
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

@@ -63,9 +63,9 @@ ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
               "target-abi)\n";
     TargetABI = ABI_Unknown;
   } else if ((ABIName.startswith("il32pc") || ABIName.startswith("l64pc")) &&
-             !FeatureBits[RISCV::FeatureCheri]) {
+             !FeatureBits[RISCV::FeatureCheriCommon]) {
     errs() << "Pure-capability ABI can't be used for a target that "
-              "doesn't support the XCheri instruction set extension (ignoring "
+              "doesn't support the CHERI instruction set extension (ignoring "
               "target-abi)\n";
     TargetABI = ABI_Unknown;
   } else if (!IsRV64 && IsRVE && TargetABI != ABI_ILP32E &&