Skip to content

Commit

Permalink
docs: fix formatting in design hierarchy documentation for clarity
Browse files Browse the repository at this point in the history
  • Loading branch information
Oron Port committed Feb 10, 2025
1 parent d2741ff commit e519a3f
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions docs/user-guide/design-hierarchy/index.md
Original file line number Diff line number Diff line change
Expand Up @@ -474,9 +474,9 @@ children = [
## Design Composition & Instantiation
DFHDL supports three mechanisms to form a design hierarchy through design instantiation and composition:

* [Direct Connection Composition][direct-connection-composition] - The most common and recommended mechanism to construct complex design hierarchies with multiple inputs and outputs. Within this mechanism, the design instantiation and port connection can be executed separately. This enables child design ports to be referenced without declaring and connecting intermediate variables.
* [Via Connection Composition][via-connection-composition] - A legacy mechanism to connect ports only within a design instantiation. This mechanism mainly exists for coexistence with the Verilog module instancing and VHDL component instancing mechanisms. The DFHDL compiler automatically transforms a direct connection composition into a via connection composition.
* [Functional Composition][functional-composition] - A method call mechanism to describe design composition. This mechanism is reserved for dataflow designs only and is mostly relevant for arithmetic/logic design functionality that has a single output port. The DFHDL compiler automatically transforms a functional composition into direct design composition.
* [Direct Connection Composition][direct-connection-composition] - The most common and recommended mechanism to construct complex design hierarchies with multiple inputs and outputs. Within this mechanism, the design instantiation and port connection can be executed separately. This enables child design ports to be referenced without declaring and connecting intermediate variables.
* [Via Connection Composition][via-connection-composition] - A legacy mechanism to connect ports only within a design instantiation. This mechanism mainly exists for coexistence with the Verilog module instancing and VHDL component instancing mechanisms. The DFHDL compiler automatically transforms a direct connection composition into a via connection composition.
* [Functional Composition][functional-composition] - A method call mechanism to describe design composition. This mechanism is reserved for dataflow designs only and is mostly relevant for arithmetic/logic design functionality that has a single output port. The DFHDL compiler automatically transforms a functional composition into direct design composition.

The following subsections dive into further details of the three design composition mechanisms. For this purpose, we continue with our running example of a bit shifter. To demonstrate composition, let's first describe a more complex shifter that has both left and right shift capabilities, as a flat (composition-less) design:

Expand Down

0 comments on commit e519a3f

Please sign in to comment.