Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

v0.9.0 update batch #186

Merged
merged 60 commits into from
Jan 10, 2025
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
60 commits
Select commit Hold shift + click to select a range
30ee721
drop output internal read for vhdl.v93
soronpo Sep 12, 2024
66264e7
cosmetic improvements and documentation to DropOutportRead
soronpo Sep 12, 2024
7f36ccd
print only changes
soronpo Sep 20, 2024
48b093f
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into docsu…
soronpo Sep 20, 2024
5f0ffd6
turn on stripMargin alignment
soronpo Sep 25, 2024
c41e85d
clearer `initFile` error message
soronpo Sep 25, 2024
19cc784
improve vector type printing
soronpo Sep 25, 2024
a5f4bdd
trap DFVal implicit conversion type runtime errors
soronpo Sep 25, 2024
d89dcc4
relax vector compile-time cell type checks and apply runtime checks
soronpo Sep 25, 2024
782a7a4
add support for nvc and iverilog
soronpo Sep 26, 2024
96c063b
add linter tool selection in DFApp
soronpo Sep 29, 2024
bfdd879
No need for specific VivadoOptions
soronpo Sep 30, 2024
3b7bd73
belongs to last commit
soronpo Sep 30, 2024
35a72aa
fix verilog 95 sensitivity list separator
soronpo Sep 30, 2024
46832d1
add QuestaSim linting support
soronpo Oct 1, 2024
ce986f3
simplify verilog printing
soronpo Oct 1, 2024
ec6c16b
suppress nvc shared variable warning within Scala execution
soronpo Oct 1, 2024
1f3381e
generalized nvc warning suppression to any shared variable name
soronpo Oct 1, 2024
6e0a68b
verilog inputs must have wire modifier
soronpo Oct 2, 2024
d7a7539
add Vivado Simulator linting support
soronpo Oct 3, 2024
3cb9b9a
running tool version checks under a temporary folder
soronpo Oct 3, 2024
e91f669
suppress nvc warning of existing folder
soronpo Oct 3, 2024
2221feb
commit and run relative paths where possible
soronpo Oct 3, 2024
d868ccb
fix missing DFApp lint tool selection propagation
soronpo Oct 3, 2024
5aa9d0c
change linter `warnAsError` to `fatalWarnings`
soronpo Oct 3, 2024
b8b4608
add DFApp fatal warnings options
soronpo Oct 4, 2024
6312a26
in case a dangling input is allowed, we fix ViaConnection stage to ha…
soronpo Oct 4, 2024
24dbf70
add dangling input port elaboration checks
soronpo Oct 4, 2024
812108b
add missing period to an error message
soronpo Oct 4, 2024
b351ca3
handle vhdl.v93 properly since it does not support unconstrained arrays
soronpo Oct 6, 2024
8d7173c
suppress vivado warnings of missing initial parameter values
soronpo Oct 6, 2024
01cc39e
allow more `FullCompileSpec` customization
soronpo Oct 6, 2024
1918169
handle verilog.v2001 and below not supporting global parameters
soronpo Oct 7, 2024
1685f1f
place `Int` parameters first in vhdl and verilog, since they may be u…
soronpo Oct 7, 2024
c0de5bf
Questa `-pedantic` mode has a bug
soronpo Oct 8, 2024
4e77203
fix vhdl vector printing so that AES Cipher compiles successfully in …
soronpo Oct 8, 2024
e53e31d
fix vhdl test
soronpo Oct 8, 2024
56e8bd8
handle ports of vectors with design-parameters under vhdl.v93 by inli…
soronpo Oct 9, 2024
156cd71
fix vhdl `to_slv` for vectors with depth > 1
soronpo Oct 9, 2024
42106e9
fix VHDL print test
soronpo Oct 14, 2024
9110233
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
Oct 22, 2024
8cdd9f3
ignore cache folder
Oct 22, 2024
8e55aa7
update docs packages
Oct 22, 2024
68f5017
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
Nov 25, 2024
196d032
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
Dec 5, 2024
acb7eee
perform port vector parameter globalization instead of inlining for v…
Dec 7, 2024
2b571ee
update Scala to 3.5.2
Dec 7, 2024
a1465f0
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
Dec 7, 2024
be7fc26
add copy functions with new references
Dec 7, 2024
9b13c2c
placing DFStruct given to DFType in a non-conflicting way
Dec 23, 2024
9ce91e5
introduce TCConv
Dec 24, 2024
1a3ebce
relax sanity refchecks for by-name references
Dec 30, 2024
4895222
fix copy of typerefs
Dec 30, 2024
6912f70
separate public members analysis
Dec 30, 2024
d16138c
update globalization with design duplications
Dec 30, 2024
add7ff5
parameter globalization now keeps the dependecy arithmetics and makin…
Jan 10, 2025
0765ff6
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
Jan 10, 2025
02fa4cb
temporarily disable CipherSpec verilog checks
Jan 10, 2025
c55e5c5
CipherSpec split to with/out user opaques
Jan 10, 2025
c36b913
add a helper summon inline method
Jan 10, 2025
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 7 additions & 1 deletion .github/workflows/build.yml
Original file line number Diff line number Diff line change
Expand Up @@ -23,10 +23,16 @@ jobs:
with:
jvm: adopt:16
apps: sbt bloop
- name: Setup Simulation Tools
- name: Setup All Simulation Tools but NVC
uses: YosysHQ/setup-oss-cad-suite@v3
- name: Setup Homebrew (for NVC)
uses: Homebrew/actions/setup-homebrew@master
- name: Setup NVC
run: brew install nvc
- run: |
verilator -version
iverilog -V
ghdl version
nvc --version
- name: Run tests
run: sbt test
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
myenv/**
out/
.idea/
.cache/
/.bsp/
project/project
project/target
Expand Down
2 changes: 2 additions & 0 deletions .scalafmt.conf
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,8 @@ runner.dialect = scala3

maxColumn = 100

assumeStandardLibraryStripMargin = true
align.stripMargin = true
rewrite.scala3.removeOptionalBraces = oldSyntaxToo
rewrite.scala3.insertEndMarkerMinLines = 15

Expand Down
2 changes: 1 addition & 1 deletion build.sbt
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ commands += DFHDLCommands.quickTestSetup

// format: off
val projectName = "dfhdl"
val compilerVersion = "3.5.1"
val compilerVersion = "3.5.2"

inThisBuild(
List(
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -406,3 +406,11 @@ extension (net: DFNet)
case DFNet(DFRef(lhs: DFVal), _, DFRef(rhs: DFVal), _, _, _) =>
lhs.collectRelMembers(false) ++ rhs.collectRelMembers(false)
case _ => Nil

extension (member: DFMember)
def isPublicMember(using MemberGetSet): Boolean =
member match
case DclPort() => true
case DesignParam(_) => true
case _: DomainBlock => true
case _ => false
4 changes: 4 additions & 0 deletions compiler/ir/src/main/scala/dfhdl/compiler/ir/Config.scala
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,10 @@ enum RTDomainCfg extends HasRefCompare[RTDomainCfg] derives CanEqual:
lazy val getRefs: List[DFRef.TwoWayAny] = this match
case Related(relatedDomainRef) => List(relatedDomainRef)
case _ => Nil

def copyWithNewRefs: this.type = this match
case Related(relatedDomainRef) => Related(relatedDomainRef.copyAsNewRef).asInstanceOf[this.type]
case _ => this
end RTDomainCfg

object RTDomainCfg:
Expand Down
49 changes: 34 additions & 15 deletions compiler/ir/src/main/scala/dfhdl/compiler/ir/DB.scala
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,8 @@ final case class DB(
val designDB: DB = self
def apply[M <: DFMember, M0 <: M](ref: DFRef[M]): M0 =
refTable(ref).asInstanceOf[M0]
def getOption[M <: DFMember, M0 <: M](ref: DFRef[M]): Option[M0] =
refTable.get(ref).asInstanceOf[Option[M0]]
def getOrigin(ref: DFRef.TwoWayAny): DFMember = originRefTable(ref)
def set[M <: DFMember](originalMember: M)(newMemberFunc: M => M): M =
newMemberFunc(originalMember)
Expand Down Expand Up @@ -60,7 +62,7 @@ final case class DB(

lazy val top: DFDesignBlock = membersNoGlobals.head match
case m: DFDesignBlock => m
case _ => throw new IllegalArgumentException("Unexpected member as Top.")
case invalidTop => throw new IllegalArgumentException(s"Unexpected member as Top:\n$invalidTop")

lazy val memberTable: Map[DFMember, Set[DFRefAny]] = refTable.invert

Expand Down Expand Up @@ -417,7 +419,7 @@ final case class DB(
if (prevNet.getOwnerDomain != net.getOwnerDomain)
newError(
s"""|Found multiple domain assignments to the same variable/port `${toDcl
.getFullName}`
.getFullName}`.
|Only variables declared as `VAR.SHARED` under ED domain allow this.
|The previous write occurred at ${prevNet.meta.position}""".stripMargin
)
Expand All @@ -428,7 +430,7 @@ final case class DB(
if (prevNet.isConnection || prevNet.isAssignment && !net.isAssignment)
newError(
s"""Found multiple connections write to the same variable/port `${toDcl
.getFullName}`
.getFullName}`.
|The previous write occurred at ${prevNet.meta.position}""".stripMargin
)
// if no previous connection in this range, we add it to the range map
Expand Down Expand Up @@ -461,7 +463,8 @@ final case class DB(
|Unable to determine directionality for the following nets:
|${pendingNets.map(_.net.meta.position).mkString("\n")}""".stripMargin
)
case Nil => connToDcls
case Nil =>
connToDcls
end match
end getConnToDcls

Expand All @@ -484,14 +487,6 @@ final case class DB(
// |Hierarchy: ${targetPort.getOwnerNamed.getFullName}""".stripMargin
// )
None
// count the hierarchy distance from inside to outside
def distance(inside: DFDesignBlock, outside: DFDesignBlock): Int =
var distance = 0
var dsn = inside
while (dsn != outside)
distance = distance + 1
dsn = dsn.getOwnerDesign
return distance
// group magnet ports according to the magnet type
val magnetDclGroups =
members.view
Expand Down Expand Up @@ -533,14 +528,18 @@ final case class DB(
port.isPortIn && !port.isSameOwnerDesignAs(targetPort) &&
targetPort.isInsideOwner(port.getOwnerDesign)
}.map { port =>
(port, distance(targetDsn, port.getOwnerDesign))
(port, targetDsn.getDistanceFromOwnerDesign(port.getOwnerDesign))
}.toList.sortBy(_._2)
// sorted source out port candidates according to the distance
val sourceOutCandidates = dclGrp.filter(_.isPortOut)
.map { port =>
val portDsn = port.getOwnerDesign
val commonDesign = targetDsn.getCommonDesignWith(portDsn)
(port, distance(targetDsn, commonDesign), distance(portDsn, commonDesign))
(
port,
targetDsn.getDistanceFromOwnerDesign(commonDesign),
portDsn.getDistanceFromOwnerDesign(commonDesign)
)
}.toList.sortBy(_._3).sortBy(_._2)
(sourceInCandidates, sourceOutCandidates) match
case (Nil, Nil) =>
Expand Down Expand Up @@ -569,7 +568,7 @@ final case class DB(
port.isPortOut && !port.isSameOwnerDesignAs(targetPort) &&
port.isInsideOwner(targetDsn)
}.map { port =>
(port, distance(port.getOwnerDesign, targetDsn))
(port, port.getDistanceFromOwnerDesign(targetDsn))
}.toList.sortBy(_._2)
sourceOutCandidates match
case Nil =>
Expand Down Expand Up @@ -603,6 +602,24 @@ final case class DB(
ret
end magnetConnectionTable

def checkDanglingInputs(): Unit =
// collect all input ports that are not connected directly or implicitly as magnets
val danglingInputs = members.collect {
case p: DFVal.Dcl
if p.isPortIn && !connectionTable.contains(p) &&
!p.getOwnerDesign.isTop && !magnetConnectionTable.contains(p) =>
val ownerDesign = p.getOwnerDesign
s"""|DFiant HDL connectivity error!
|Position: ${ownerDesign.meta.position}
|Hierarchy: ${ownerDesign.getFullName}
|Message: Found a dangling (unconnected) input port `${p.getName}`.""".stripMargin
}
if (danglingInputs.nonEmpty)
throw new IllegalArgumentException(
danglingInputs.mkString("\n")
)
end checkDanglingInputs

// holds for each RTDomain/RTDesign/RTInterface that its configuration on another domain,
// the domain it is dependent on
lazy val dependentRTDomainOwners: Map[DFDomainOwner, DFDomainOwner] =
Expand Down Expand Up @@ -788,6 +805,7 @@ final case class DB(
nameCheck()
connectionTable // causes connectivity checks
magnetConnectionTable // causes magnet connectivity checks
checkDanglingInputs()
directRefCheck()
circularDerivedDomainsCheck()

Expand Down Expand Up @@ -833,6 +851,7 @@ enum MemberView derives CanEqual:
trait MemberGetSet:
def designDB: DB
def apply[M <: DFMember, M0 <: M](ref: DFRef[M]): M0
def getOption[M <: DFMember, M0 <: M](ref: DFRef[M]): Option[M0]
def getOrigin(ref: DFRef.TwoWayAny): DFMember
def set[M <: DFMember](originalMember: M)(newMemberFunc: M => M): M
def replace[M <: DFMember](originalMember: M)(newMember: M): M
Expand Down
Loading
Loading