A simple digital datapath is implemented using two pieces of Software: Quartus Prime, which is produced by Intel, and ModelSim (Lite Version), which is produced by Mentor Graphics. Through the use of SystemVerilog, which is a Hardware Description Language (HDL), this design is loaded onto a DE1-SoC FPGA board.
These were illustrated prior to the actual design of the circuit in order to be able to create a Finite State Machine (FSM) Controller in the (statemachine.sv) file.
The 7-Segment Display on the De1-SoC is driven by active-low HEX outputs (i.e. 0 values turn the segment ON and 1 values turn the segment OFF.) However, the Loop Count on the LEDR outputs are active-high. For our purposes, we will encode this in the LEDR Driver in the (driver.sv) file as a 10-bit one-hot signal.
| 7-Segment Display | Code |
|---|---|
| C | 7'b1000110 |
| P | 7'b0001100 |
| E | 7'b0000110 |
| n | 7'b1001000 |
| 3 | 7'b0110000 |
| 1 | 7'b1111001 |
| b | 7'b0000011 |
| y | 7'b0010001 |
| e | 7'b0000100 |
Based on previous knowledge of similar digital datapaths, the top level diagram of was created as shown below.
The controller of the circuit will be transitioning through a series of states. The outputs are dependent on the current state, whereas the next state is determined by the current state, as well as input and outputs.
The current state will be changing on every positive clock edge if the active-high reset signal is asserted (i.e. sequential, synchronous). The outputs and next state are driven by combinational logic and are changed through "blocking" assignments so that they take effect in series.
| Current State | Next State | Conditions |
|---|---|---|
| X | ResetState | (resetb == 1) && (posedge clock) |
| ResetState | HardwareOffState | (resetb == 0) && (posedge clock) |
| HardwareOffState | DisplayCase_A_State | (resetb == 0) && (posedge clock) |
| DisplayCase_A_State | DisplayCase_B_J_State | (resetb == 0) && (posedge clock) |
| DisplayCase_B_J_State ... | ... DisplayCase_E_M_State | (resetb == 0) && (posedge clock) |
| DisplayCase_E_M_State | DisplayCase_F_State | (resetb == 0) && (posedge clock) && (LEDR < {10{1'b1}}) |
| DisplayCase_E_M_State | DisplayCase_N_State | (resetb == 0) && (posedge clock) && (LEDR == {10{1'b1}}) |
| DisplayCase_F_State ... | ... DisplayCase_I_State | (resetb == 0) && (posedge clock) |
| DisplayCase_I_State | DisplayCase_B_J_State | (resetb == 0) && (posedge clock) |
| DisplayCase_N_State ... | ... DisplayCase_Q_State | (resetb == 0) && (posedge clock) |
| DisplayCase_Q_State | DisplayCase_R_State | (resetb == 0) && (posedge clock) |
| DisplayCase_R_State | DisplayCase_S_V_State | (resetb == 0) && (posedge clock) && (LEDR != {10{1'b1}}) |
| DisplayCase_R_State | DisplayCase_R_State | (resetb == 0) && (posedge clock) && (LEDR == {10{1'b1}}) |
| DisplayCase_S_V_State ... | ... DisplayCase_U_X_State | (resetb == 0) && (posedge clock) |
| DisplayCase_U_X_State | DisplayCase_Y_State | (resetb == 0) && (posedge clock) |
| DisplayCase_Y_State ... | ... DisplayCase_c_State | (resetb == 0) && (posedge clock) |
| Displaycase_c_State | DisplayCase_R_State | (resetb == 0) && (posedge clock) |
The HEX0 ... HEX5 Displays are instantiated as modified 7-bit registers, which default to turn the respective 7-Segment Display off on active-high reset. The LEDR Driver is a heavily modified 10-bit register, which increments a 10-bit one hot bus as the message loops through the DE1-SoC FPGA.
There is also a Flickering Light Effect that is implemented on completion of 10 loops around the board.
Multiple tests have been implemented to ensure the circuit is functioning exactly as intended. These are evaluated through simulation and loading the design onto the physical DE1-SoC FPGA board.
For each of the .sv files included in this project, a corresponding testbench was written to cycle the clock and thoroughly evaluate the functioning of the inputs and outputs. Our testbench modules have no input and output ports. They instead instantiate the corresponding synthesizable SystemVerilog module. The testbench drives the clock with the Verilog delay syntax (#).
We tried our best to exhaustively test our SystemVerilog Register Transfer Level (RTL) code. To exercise the entire Design Under Test (DUT), we use the (Verilog $display) tasks to check whether our signals are the expected value.
These testbenches were simulated on Modelsim in a very lengthy procedure involving clock-timing to check if the relevant signals are updated on the positive clock edges. These are implemented in the tb_ ... .sv files to make debugging the RTL a smoother process.
This was developed by The University of British Columbia Electrical and Computer Engineering Department as an emulator. It allows a visual representation of the functionality of the real board (i.e. buttons, LEDs, HEX Displays). More detail is provided in the de1-gui directory.
For our purposes, we have instantiated this in our (tb_toplevel.sv) file to try our best at manifesting the actual DE1-SoC FPGA board.
The (toplevel.vo) file is generated from the Quartus project compilation in the (.../modelsim) directory.
The cyclonev_ver, altera_ver, altera_lnsim_ver, altera_mf_ver are added to Modelsim when simulating (tb_toplevel.sv) to instantiates primitive FPGA modules like cyclone_lcell_comb and cyclone_io_ibuf.
A project is created using Quartus Prime software to load the .sv files onto the DE1-SoC FPGA board. The board must be specified in the Project Wizard and the pin assignments must be imported from the (DE1_SoC.qsf) file and copied into the (toplevel.qsf) file. This step is crucial to avoid damaging the $200 piece of equipment. Following this step, the Start Compilation tool is run over the duration of several minutes. Using the Programmer tool, the design is downloaded onto the DE1-SoC FPGA board via JTAG.
The videos in the demonstrations directory show the end result of this procedure as well as the output on the DE1-SoC FPGA. This directory is tracked using Git LFS due to size restrictions. We have embedded low resolution compressed versions of these files below.
Compressed_Quartus.mp4
Compressed_DE1-Soc.mp4
The idea for this project was derived from The University of British Columbia Electrical and Computer Engineering Undergraduate program. The APSC 160 - Introduction to Computation and CPEN 311 - Digital Systems Design course requirements involve two individual projects which acted as the inspiration for this circuit. A Scrolling 'HELLO' Display originally created using C Programming concepts in APSC 160 was redesigned through the use of Digital Design concepts from a Baccarat engine created in CPEN 311.
The project has been heavily refactored from the initial design to make the StateMachine and testbench more seamless. The entire design document is included in the (design.pdf) file.