Merge branch 'master' into i2154-android64-base-address

clients/drcachesim/docs/drcachesim.dox.in

@@ -1084,17 +1084,19 @@ All markers of the original trace are present, except for:
 - #dynamorio::drmemtrace::TRACE_MARKER_TYPE_SYSCALL_TRACE_END
 - #dynamorio::drmemtrace::TRACE_MARKER_TYPE_SYSCALL_FAILED
 - #dynamorio::drmemtrace::TRACE_MARKER_TYPE_SIGNAL_NUMBER
+
 Which have been removed.
+
 Because tracing overhead results into inflated context switches, the
 #dynamorio::drmemtrace::TRACE_MARKER_TYPE_CPU_ID values have been modified to
 "unknown CPU" to avoid confusion. We recommend users to use our scheduler
 (see \ref sec_drcachesim_sched) for a realistic schedule of a trace's threads.
-Also, we preserved the following markers:
+
+Also, we preserved the following markers, but only for SYS_futex functions:
 - #dynamorio::drmemtrace::TRACE_MARKER_TYPE_FUNC_ID
 - #dynamorio::drmemtrace::TRACE_MARKER_TYPE_FUNC_ARG
 - #dynamorio::drmemtrace::TRACE_MARKER_TYPE_FUNC_RETVAL
 - #dynamorio::drmemtrace::TRACE_MARKER_TYPE_FUNC_RETADDR
-But only for SYS_futex functions.
 
 Finally, every trace has a v2p.textproto file associated to it, which provides a
 plausible virtual to physical mapping of the virtual addresses present in a trace
@@ -1109,14 +1111,14 @@ These traces are supported starting from DynamoRIO 11.3.
 
 The Google Workload Traces can be downloaded from:
 
- - [Google workload trace folder](https://console.cloud.google.com/storage/browser/external-traces-v2)
+- [Google workload trace folder](https://console.cloud.google.com/storage/browser/external-traces-v2)
 
 Directory structure:
-- \verbatim
-  workload_name/
-    <uuid>.<tid>.memtrace.zip
-    v2p.textproto
-  \endverbatim
+\verbatim
+workload_name/
+  <uuid>.<tid>.memtrace.zip
+  v2p.textproto
+\endverbatim
 
 \section sec_google_help Getting Help and Reporting Bugs
 
@@ -1156,8 +1158,8 @@ You can contribute to the project in many ways:
 If you would like to cite this work, you can use the following BibTeX entry:
 
 \verbatim
-@misc{ Google_Workload_Traces_Version_2,
-  title = {{Google Workload Traces Version 2}},
+@misc{Google_Workload_Traces_Version_2,
+  title = {Google Workload Traces Version 2},
   howpublished = {\url{https://console.cloud.google.com/storage/browser/external-traces-v2}},
   note = {Accessed: yyyy-mm-dd}
 }

core/arch/aarch64/proc.c

@@ -36,12 +36,44 @@
 #include "arch.h"
 #include "instr.h"
 
+#if defined(MACOS)
+#    include <sys/sysctl.h>
+#endif
+
 static int num_simd_saved;
 static int num_simd_registers;
 static int num_svep_registers;
 static int num_ffr_registers;
 static int num_opmask_registers;
 
+#define GET_FEAT_REG(FEATURE) (feature_reg_idx_t)((((ushort)FEATURE) & 0x3F00) >> 8)
+#define GET_FEAT_NIBPOS(FEATURE) ((((ushort)FEATURE) & 0x00F0) >> 4)
+#define GET_FEAT_VAL(FEATURE) (((ushort)FEATURE) & 0x000F)
+#define GET_FEAT_NSFLAG(FEATURE) ((((ushort)FEATURE) & 0x8000) >> 15)
+#define GET_FEAT_EXACT_MATCH(FEATURE) ((((ushort)FEATURE) & 0x4000) >> 14)
+
+void
+proc_set_feature(feature_bit_t feature_bit, bool enable)
+{
+    uint64 *freg_val = cpu_info.features.isa_features;
+    ushort feat_nibble = GET_FEAT_NIBPOS(feature_bit);
+    bool feat_nsflag = GET_FEAT_NSFLAG(feature_bit);
+    uint64 feat_val = GET_FEAT_VAL(feature_bit);
+
+    feature_reg_idx_t feat_reg = GET_FEAT_REG(feature_bit);
+    freg_val += feat_reg;
+
+    /* Clear the current feature state. */
+    *freg_val &= ~(0xFULL << (feat_nibble * 4));
+    if (enable) {
+        /* Write the feature value into the feature nibble. */
+        *freg_val |= feat_val << (feat_nibble * 4);
+    } else if (feat_nsflag) {
+        /* If the not-set flag is 0xF, then that needs manually setting. */
+        *freg_val |= 0xF << (feat_nibble * 4);
+    }
+}
+
 #ifndef DR_HOST_NOT_TARGET
 
 #    define NUM_FEATURE_REGISTERS (sizeof(features_t) / sizeof(uint64))
@@ -86,7 +118,7 @@ read_feature_regs(uint64 isa_features[])
         : "x0");
 }
 
-#    if !defined(MACOS) // TODO i#5383: Get this working on Mac. */
+#    if !defined(MACOS)
 static void
 get_processor_specific_info(void)
 {
@@ -146,6 +178,32 @@ get_processor_specific_info(void)
     dr_set_vector_length(256);
 #        endif
 }
+#    else /* defined(MACOS) */
+
+/* On macOS, MRS appears to be restricted. We'll use sysctl's instead.
+ * XXX i#5383: Add remaining features from other sysctls.
+ */
+static void
+get_processor_specific_info(void)
+{
+    memset(&cpu_info.features, 0, sizeof(cpu_info.features));
+
+#        define SET_FEAT_IF_SYSCTL_EQ(FEATURE, SYSCTL, TY, VAL)                         \
+            TY FEATURE##_tmp;                                                           \
+            size_t FEATURE##_tmp_buflen = sizeof(FEATURE##_tmp);                        \
+            if (sysctlbyname(SYSCTL, &FEATURE##_tmp, &FEATURE##_tmp_buflen, NULL, 0) == \
+                -1) {                                                                   \
+                ASSERT_CURIOSITY(false && SYSCTL " sysctl failed");                     \
+                SYSLOG_INTERNAL_WARNING("Failed to read " SYSCTL " sysctl");            \
+            } else if (FEATURE##_tmp_buflen == sizeof(FEATURE##_tmp)) {                 \
+                if (FEATURE##_tmp == VAL) {                                             \
+                    proc_set_feature(FEATURE, true);                                    \
+                }                                                                       \
+            }
+
+    SET_FEAT_IF_SYSCTL_EQ(FEATURE_PAUTH, "hw.optional.arm.FEAT_PAuth", uint32_t, 1);
+    SET_FEAT_IF_SYSCTL_EQ(FEATURE_FPAC, "hw.optional.arm.FEAT_FPAC", uint32_t, 1);
+}
 #    endif
 
 #    define LOG_FEATURE(feature)       \
@@ -172,7 +230,6 @@ proc_init_arch(void)
     }
 
 #ifndef DR_HOST_NOT_TARGET
-#    if !defined(MACOS) // TODO i#5383: Get this working on Mac. */
     get_processor_specific_info();
 
     DOLOG(1, LOG_TOP, {
@@ -247,38 +304,9 @@ proc_init_arch(void)
             cpu_info.features.isa_features[AA64MMFR2]);
         LOG_FEATURE(FEATURE_LSE2);
     });
-#    endif
 #endif
 }
 
-#define GET_FEAT_REG(FEATURE) (feature_reg_idx_t)((((ushort)FEATURE) & 0x3F00) >> 8)
-#define GET_FEAT_NIBPOS(FEATURE) ((((ushort)FEATURE) & 0x00F0) >> 4)
-#define GET_FEAT_VAL(FEATURE) (((ushort)FEATURE) & 0x000F)
-#define GET_FEAT_NSFLAG(FEATURE) ((((ushort)FEATURE) & 0x8000) >> 15)
-#define GET_FEAT_EXACT_MATCH(FEATURE) ((((ushort)FEATURE) & 0x4000) >> 14)
-
-void
-proc_set_feature(feature_bit_t feature_bit, bool enable)
-{
-    uint64 *freg_val = cpu_info.features.isa_features;
-    ushort feat_nibble = GET_FEAT_NIBPOS(feature_bit);
-    bool feat_nsflag = GET_FEAT_NSFLAG(feature_bit);
-    uint64 feat_val = GET_FEAT_VAL(feature_bit);
-
-    feature_reg_idx_t feat_reg = GET_FEAT_REG(feature_bit);
-    freg_val += feat_reg;
-
-    /* Clear the current feature state. */
-    *freg_val &= ~(0xFULL << (feat_nibble * 4));
-    if (enable) {
-        /* Write the feature value into the feature nibble. */
-        *freg_val |= feat_val << (feat_nibble * 4);
-    } else if (feat_nsflag) {
-        /* If the not-set flag is 0xF, then that needs manually setting. */
-        *freg_val |= 0xF << (feat_nibble * 4);
-    }
-}
-
 void
 enable_all_test_cpu_features()
 {

core/iox.h

@@ -706,9 +706,7 @@ TNAME(d_r_vsnprintf)(TCHAR *s, size_t max, const TCHAR *fmt, va_list ap)
             c++;
         } else {
             const TCHAR *cstart = c;
-            int nbytes = 0;
             while (*c && *c != _T('%')) {
-                nbytes++;
                 c++;
             }
             while (cstart < c) {

core/ir/aarch64/codec.c

@@ -283,6 +283,10 @@ decode_sysreg(uint imm15)
 {
     reg_t sysreg;
     switch (imm15) {
+    case 0x4681: sysreg = DR_REG_CONTEXTIDR_EL1; break;
+    case 0x4201: sysreg = DR_REG_ELR_EL1; break;
+    case 0x4200: sysreg = DR_REG_SPSR_EL1; break;
+    case 0x4684: sysreg = DR_REG_TPIDR_EL1; break;
     case 0x4000: sysreg = DR_REG_MIDR_EL1; break;
     case 0x4005: sysreg = DR_REG_MPIDR_EL1; break;
     case 0x4006: sysreg = DR_REG_REVIDR_EL1; break;
@@ -419,6 +423,10 @@ encode_sysreg(OUT uint *imm15, opnd_t opnd)
 {
     if (opnd_is_reg(opnd)) {
         switch (opnd_get_reg(opnd)) {
+        case DR_REG_CONTEXTIDR_EL1: *imm15 = 0x4681; break;
+        case DR_REG_ELR_EL1: *imm15 = 0x4201; break;
+        case DR_REG_SPSR_EL1: *imm15 = 0x4200; break;
+        case DR_REG_TPIDR_EL1: *imm15 = 0x4684; break;
         case DR_REG_MIDR_EL1: *imm15 = 0x4000; break;
         case DR_REG_MPIDR_EL1: *imm15 = 0x4005; break;
         case DR_REG_REVIDR_EL1: *imm15 = 0x4006; break;

core/ir/aarch64/encode.c

@@ -122,7 +122,7 @@ const char *const reg_names[] = {
     "id_aa64pfr0_el1", "id_aa64mmfr1_el1", "id_aa64dfr0_el1", "id_aa64zfr0_el1",
     "id_aa64pfr1_el1", "id_aa64mmfr2_el1", "midr_el1", "mpidr_el1", "revidr_el1",
 
-    "fpmr",
+    "fpmr", "contextidr_el1", "elr_el1", "spsr_el1", "tpidr_el1"
 };
 
 
@@ -203,7 +203,8 @@ const reg_id_t dr_reg_fixer[] = { REG_NULL,
     DR_REG_ID_AA64DFR0_EL1, DR_REG_ID_AA64ZFR0_EL1, DR_REG_ID_AA64PFR1_EL1,
     DR_REG_ID_AA64MMFR2_EL1, DR_REG_MIDR_EL1, DR_REG_MPIDR_EL1, DR_REG_REVIDR_EL1,
 
-    DR_REG_FPMR,
+    DR_REG_FPMR, DR_REG_CONTEXTIDR_EL1, DR_REG_ELR_EL1, DR_REG_SPSR_EL1,
+    DR_REG_TPIDR_EL1
 };
 
 /* Maps real ISA registers to their corresponding virtual DR_ISA_REGDEPS register.
@@ -392,6 +393,10 @@ const reg_id_t d_r_reg_id_to_virtual[] = {
     DR_REG_VIRT208, /* DR_REG_REVIDR_EL1 */
 
     DR_REG_VIRT209, /* DR_REG_FPMR */
+    DR_REG_VIRT210, /* DR_REG_CONTEXTIDR_EL1 */
+    DR_REG_VIRT211, /* DR_REG_ELR_EL1 */
+    DR_REG_VIRT212, /* DR_REG_SPSR_EL1 */
+    DR_REG_VIRT213, /* DR_REG_TPIDR_EL1 */
 };
 /* clang-format on */
 

core/ir/opnd_api.h

@@ -1061,6 +1061,10 @@ enum {
     DR_REG_MPIDR_EL1,        /**< The "mpidr_el1" register. */
     DR_REG_REVIDR_EL1,       /**< The "revidr_el1" register. */
     DR_REG_FPMR,             /**< The "fpmr" register. */
+    DR_REG_CONTEXTIDR_EL1,   /**< The "contextidr_el1" register. */
+    DR_REG_ELR_EL1,          /**< The "elr_el1" register. */
+    DR_REG_SPSR_EL1,         /**< The "spsr_el1" register. */
+    DR_REG_TPIDR_EL1,        /**< The "tpidr_el1" register. */
 #    endif
 
 /* Aliases below here: */
@@ -1117,12 +1121,12 @@ enum {
     /** Thread Pointer/ID Register, Read-Only, EL0. */
     DR_REG_TPIDRRO_EL0 = DR_REG_TPIDRURO,
     /* ARMv7 Thread Registers */
-    DR_REG_CP15_C13_2 = DR_REG_TPIDRURW,  /**< User Read/Write Thread ID Register */
-    DR_REG_CP15_C13_3 = DR_REG_TPIDRURO,  /**< User Read-Only Thread ID Register */
+    DR_REG_CP15_C13_2 = DR_REG_TPIDRURW,       /**< User Read/Write Thread ID Register */
+    DR_REG_CP15_C13_3 = DR_REG_TPIDRURO,       /**< User Read-Only Thread ID Register */
 
 #    ifdef AARCH64
-    DR_REG_LAST_VALID_ENUM = DR_REG_FPMR, /**< Last valid register enum */
-    DR_REG_LAST_ENUM = DR_REG_FPMR,       /**< Last value of register enums */
+    DR_REG_LAST_VALID_ENUM = DR_REG_TPIDR_EL1, /**< Last valid register enum */
+    DR_REG_LAST_ENUM = DR_REG_TPIDR_EL1,       /**< Last value of register enums */
 #    else
     DR_REG_LAST_VALID_ENUM = DR_REG_TPIDRURO, /**< Last valid register enum */
     DR_REG_LAST_ENUM = DR_REG_TPIDRURO,       /**< Last value of register enums */

core/ir/opnd_shared.c

@@ -2782,7 +2782,7 @@ reg_get_size(reg_id_t reg)
     }
     if ((reg >= DR_REG_P0 && reg <= DR_REG_P15) || reg == DR_REG_FFR)
         return OPSZ_SVE_PREDLEN_BYTES;
-    if (reg >= DR_REG_CNTVCT_EL0 && reg <= DR_REG_FPMR)
+    if (reg >= DR_REG_CNTVCT_EL0 && reg <= DR_REG_TPIDR_EL1)
         return OPSZ_8;
     if (reg >= DR_REG_NZCV && reg <= DR_REG_FPSR)
         return OPSZ_8;

core/unix/os.c

@@ -784,7 +784,7 @@ static init_fn_t
 #else
 /* If we're a normal shared object, then we override _init.
  */
-int
+INITIALIZER_ATTRIBUTES int
 _init(int argc, char **argv, char **envp)
 {
 #    ifdef ANDROID
@@ -1143,6 +1143,8 @@ get_application_name_helper(bool ignore_cache, bool full_path)
 #else
             /* OSX kernel puts full app exec path above envp */
             char *c, **env = our_environ;
+            ASSERT(our_environ != NULL &&
+                   "our_environ is not set in get_application_name_helper");
             do {
                 env++;
             } while (*env != NULL);

core/unix/os_public.h

@@ -242,4 +242,14 @@ typedef kernel_sigcontext_t sigcontext_t;
 #    define SC_RETURN_REG SC_A0
 #endif /* X86/ARM */
 
+/* XXX i#5383: macOS 14.4 on ARM64 _init does not seem to get called
+ * without __attribute__((constructor)) but it inexplicably breaks tests if
+ * we add this flag on X86. So we add it only on ARM64 for now.
+ */
+#if defined(MACOS) && defined(AARCH64)
+#    define INITIALIZER_ATTRIBUTES __attribute__((constructor))
+#else
+#    define INITIALIZER_ATTRIBUTES
+#endif
+
 #endif /* _OS_PUBLIC_H_ 1 */

core/unix/preload.c

@@ -50,6 +50,7 @@
 #include "configure.h"
 #include "globals_shared.h"
 #include "../config.h"
+#include "os_public.h"
 #include <stdio.h>
 /* for getpid */
 #include <unistd.h>
@@ -137,7 +138,7 @@ take_over(const char *pname)
     return true;
 }
 
-int
+INITIALIZER_ATTRIBUTES int
 #if INIT_BEFORE_LIBC
 _init(int argc, char *arg0, ...)
 {

core/unix/signal_macos.c

@@ -157,8 +157,17 @@ sigcontext_to_mcontext_simd(priv_mcontext_t *mc, sig_full_cxt_t *sc_full)
         return;
     mc->fpsr = fpc->__fpsr;
     mc->fpcr = fpc->__fpcr;
-    ASSERT(sizeof(mc->simd) == sizeof(fpc->__v));
-    memcpy(&mc->simd, &fpc->__v, sizeof(mc->simd));
+    if (proc_has_feature(FEATURE_SVE)) {
+        /* XXX i#5383: SVE and SVE2 support for MACOS still missing.
+         */
+        ASSERT_NOT_IMPLEMENTED(false);
+    } else {
+        /* ARM_NEON64 case.
+         */
+        for (int i = 0; i < proc_num_simd_registers(); i++) {
+            memcpy(&mc->simd[i].q, &fpc->__v[i], sizeof(mc->simd->q));
+        }
+    }
 #elif defined(X86)
     /* We assume that _STRUCT_X86_FLOAT_STATE* matches exactly the first
      * half of _STRUCT_X86_AVX_STATE*, and similarly for AVX and AVX512.
@@ -200,8 +209,17 @@ mcontext_to_sigcontext_simd(sig_full_cxt_t *sc_full, priv_mcontext_t *mc)
         return;
     fpc->__fpsr = mc->fpsr;
     fpc->__fpcr = mc->fpcr;
-    ASSERT(sizeof(mc->simd) == sizeof(fpc->__v));
-    memcpy(&fpc->__v, &mc->simd, sizeof(mc->simd));
+    if (proc_has_feature(FEATURE_SVE)) {
+        /* XXX i#5383: SVE and SVE2 support for MACOS still missing.
+         */
+        ASSERT_NOT_IMPLEMENTED(false);
+    } else {
+        /* ARM_NEON64 case.
+         */
+        ASSERT((sizeof(mc->simd->q) * proc_num_simd_registers()) == sizeof(fpc->__v));
+        for (int i = 0; i < proc_num_simd_registers(); i++)
+            memcpy(&fpc->__v[i], &mc->simd[i].q, sizeof(fpc->__v[i]));
+    }
 #elif defined(X86)
     sigcontext_t *sc = sc_full->sc;
     int i;

ext/drx/drx.c

@@ -71,7 +71,8 @@
 #    define IF_WINDOWS_ELSE(x, y) (y)
 #endif
 
-#if defined(X86) || defined(AARCH64)
+/* XXX i#5383: PLATFORM_SUPPORTS_SCATTER_GATHER is broken on aarch64 macOS. */
+#if (defined(X86) || defined(AARCH64)) && !(defined(MACOS) && defined(AARCH64))
 #    define PLATFORM_SUPPORTS_SCATTER_GATHER
 #endif