Version 18

hisparc.ews/design/DISCRIMINATORS/a0/a0.vhd → hisparc.ews/design/DISCRIMINATORS/a0/a0.vhd.bk!

@@ -358,7 +358,7 @@ begin
     if SYSRST = '1' then
       EXT_TR <= '0';
     elsif (CLK200MHz'event and CLK200MHz = '1') then
-      if EXT_TR_IN_DEL1 = '1' and EXT_TR_IN_DEL2 = '0' then -- On an upgoing egde of EXT_TR_IN
+      if EXT_TR_IN_DEL1 = '1' and EXT_TR_IN_DEL2 = '0' then -- On an upgoing egde of EXT_TR_IN 
         EXT_TR <= '1';
       elsif EXT_TR_CNT = COINC_TIME - 1 then
         EXT_TR <= '0';

hisparc.ews/design/DUAL_PORT_RAM/a0/a0.vhd

@@ -1,24 +1,27 @@
 -- EASE/HDL begin --------------------------------------------------------------
--- Architecture 'a0' of 'DUAL_PORT_RAM.
+-- 
+-- Architecture 'a0' of entity 'DUAL_PORT_RAM'.
+-- 
 --------------------------------------------------------------------------------
--- Copy of the interface declaration of Entity 'DUAL_PORT_RAM' :
+-- 
+-- Copy of the interface declaration:
 -- 
 --   port(
 --     DATA_IN    : in     std_logic_vector(11 downto 0);
 --     DATA_OUT   : out    std_logic_vector(11 downto 0);
 --     RDCLOCK    : in     std_logic;
---     RD_ADDRESS : in     integer range 2020 downto 0;
+--     RD_ADDRESS : in     integer range 2040 downto 0;
 --     WE         : in     std_logic;
 --     WRCLOCK    : in     std_logic;
---     WR_ADDRESS : in     integer range 2020 downto 0);
+--     WR_ADDRESS : in     integer range 2040 downto 0);
 -- 
 -- EASE/HDL end ----------------------------------------------------------------
 
 architecture a0 of DUAL_PORT_RAM is
 
-  type MEM is array(0 to 2020) of std_logic_vector(11 downto 0);
+  type MEM is array(0 to 2040) of std_logic_vector(11 downto 0);
   signal RAM_BLOCK : MEM;
-  signal RD_ADDRESS_REG : integer range 0 to 2020;
+  signal RD_ADDRESS_REG : integer range 0 to 2040;
 
 begin
 

hisparc.ews/design/DUAL_PORT_RAM/a0/a0.vhd.bk!

@@ -0,0 +1,43 @@
+-- EASE/HDL begin --------------------------------------------------------------
+-- Architecture 'a0' of 'DUAL_PORT_RAM.
+--------------------------------------------------------------------------------
+-- Copy of the interface declaration of Entity 'DUAL_PORT_RAM' :
+-- 
+--   port(
+--     DATA_IN    : in     std_logic_vector(11 downto 0);
+--     DATA_OUT   : out    std_logic_vector(11 downto 0);
+--     RDCLOCK    : in     std_logic;
+--     RD_ADDRESS : in     integer range 2020 downto 0;
+--     WE         : in     std_logic;
+--     WRCLOCK    : in     std_logic;
+--     WR_ADDRESS : in     integer range 2020 downto 0);
+-- 
+-- EASE/HDL end ----------------------------------------------------------------
+
+architecture a0 of DUAL_PORT_RAM is
+
+  type MEM is array(0 to 2020) of std_logic_vector(11 downto 0);
+  signal RAM_BLOCK : MEM;
+  signal RD_ADDRESS_REG : integer range 0 to 2020;
+
+begin
+
+  process (WRCLOCK)
+  begin
+    if (WRCLOCK'event and WRCLOCK = '1') then
+      if (WE = '1') then
+        RAM_BLOCK(WR_ADDRESS) <= DATA_IN;
+      end if;
+    end if;
+  end process;
+
+  process (RDCLOCK)
+  BEGIN
+    if (RDCLOCK'event and RDCLOCK = '1') then
+      DATA_OUT <= RAM_BLOCK(RD_ADDRESS_REG);
+      RD_ADDRESS_REG <= RD_ADDRESS;
+    end if;
+  end process;
+
+end architecture a0 ; -- of DUAL_PORT_RAM
+

hisparc.ews/design/DUMMIES/a0/a0.vhd

@@ -1,19 +1,21 @@
 -- EASE/HDL begin --------------------------------------------------------------
--- Architecture 'a0' of 'DUMMIES.
+-- 
+-- Architecture 'a0' of entity 'DUMMIES'.
+-- 
 --------------------------------------------------------------------------------
--- Copy of the interface declaration of Entity 'DUMMIES' :
+-- 
+-- Copy of the interface declaration:
 -- 
 --   port(
---     ADC_1_NEG_OR : in     std_logic;
---     ADC_1_POS_OR : in     std_logic;
---     ADC_2_NEG_OR : in     std_logic;
---     ADC_2_POS_OR : in     std_logic;
---     LED4         : out    std_logic;
---     LED5         : out    std_logic;
---     LED6         : out    std_logic;
---     LED7         : out    std_logic;
---     LED8         : out    std_logic;
---     LED9         : out    std_logic);
+--     CLK10MHz   : in     std_logic;
+--     INTF1_IO   : in     std_logic_vector(2 downto 0);
+--     INTF2_IO   : in     std_logic_vector(7 downto 0);
+--     LED4       : out    std_logic;
+--     LED5       : out    std_logic;
+--     LED6       : out    std_logic;
+--     LED7       : out    std_logic;
+--     SYSRST     : in     std_logic;
+--     USB_nPWREN : in     std_logic);
 -- 
 -- EASE/HDL end ----------------------------------------------------------------
 
@@ -26,12 +28,10 @@ begin
 -- LED1 is used for SLAVE_PRESENT
 -- LED2 is used for MASTER (GPS PRESENT)
 -- LED3 is used for COINC
-  LED4 <= '1';
-  LED5 <= '1';
-  LED6 <= '1';
-  LED7 <= '1';
-  LED8 <= '1';
-  LED9 <= '1';
+  LED4 <= '0';
+  LED5 <= '0';
+  LED6 <= '0';
+  LED7 <= '0';
 
 end architecture a0 ; -- of DUMMIES
 

hisparc.ews/design/FAKE_DATA_GEN/rtl/rtl.vhd.bk!

@@ -0,0 +1,52 @@
+-- EASE/HDL begin --------------------------------------------------------------
+-- Architecture 'rtl' of 'FAKE_DATA_GEN.
+--------------------------------------------------------------------------------
+-- Copy of the interface declaration of Entity 'FAKE_DATA_GEN' :
+-- 
+--   port(
+--     CLK200MHz     : in     std_logic;
+--     FAKE_DATA_NEG : out    std_logic_vector(11 downto 0);
+--     FAKE_DATA_POS : out    std_logic_vector(11 downto 0);
+--     SYSRST        : in     std_logic);
+-- 
+-- EASE/HDL end ----------------------------------------------------------------
+
+architecture rtl of FAKE_DATA_GEN is
+
+signal DATA_PLUS_TWO: std_logic_vector(11 downto 0);
+signal FAKE_DATA_POS_TMP: std_logic_vector(11 downto 0);
+
+begin
+
+-- Fake data generator
+-- Increment positive fake data by two
+  DATA_PLUS_TWO(0) <= '0';
+  FAKE_DATA_POS <= FAKE_DATA_POS_TMP;
+
+  process(CLK200MHz,SYSRST)
+  begin
+    if SYSRST = '1' then
+      DATA_PLUS_TWO(11 downto 1) <= (others => '0');
+    elsif (CLK200MHz'event and CLK200MHz = '1') then
+      DATA_PLUS_TWO(11 downto 1) <= DATA_PLUS_TWO(11 downto 1) + "00000000001";
+    end if;
+  end process;
+
+-- Take over DATA_PLUS_TWO on positive edge to get FAKE_DATA_POS
+  process(CLK200MHz)
+  begin
+    if (CLK200MHz'event and CLK200MHz = '1') then
+      FAKE_DATA_POS_TMP <= DATA_PLUS_TWO;
+    end if;
+  end process;
+
+-- Increment FAKE_DATA_POS by one
+  process(CLK200MHz)
+  begin
+    if (CLK200MHz'event and CLK200MHz = '0') then -- negative edge
+      FAKE_DATA_NEG <= FAKE_DATA_POS_TMP + "000000000001";
+    end if;
+  end process;
+
+end architecture rtl ; -- of FAKE_DATA_GEN
+

hisparc.ews/design/LED_DRIVER/a0/a0.vhd

@@ -1,13 +1,16 @@
 -- EASE/HDL begin --------------------------------------------------------------
--- Architecture 'a0' of 'LED_DRIVER.
+-- 
+-- Architecture 'a0' of entity 'LED_DRIVER'.
+-- 
 --------------------------------------------------------------------------------
--- Copy of the interface declaration of Entity 'LED_DRIVER' :
+-- 
+-- Copy of the interface declaration:
 -- 
 --   port(
 --     CLK10MHz : in     std_logic;
 --     INP      : in     std_logic;
---     SYSRST   : in     std_logic;
---     nOUTP    : out    std_logic);
+--     OUTP     : out    std_logic;
+--     SYSRST   : in     std_logic);
 -- 
 -- EASE/HDL end ----------------------------------------------------------------
 
@@ -30,7 +33,7 @@ begin
     end if;
   end process;
 
-  nOUTP <= '0' when (LEDSHINE_COUNTER /= "111111111111111111111") else '1';
+  OUTP <= '1' when (LEDSHINE_COUNTER /= "111111111111111111111") else '0';
 
 end architecture a0 ; -- of LED_DRIVER
 

hisparc.ews/design/LED_DRIVER/a0/a0.vhd.bk!

@@ -0,0 +1,36 @@
+-- EASE/HDL begin --------------------------------------------------------------
+-- Architecture 'a0' of 'LED_DRIVER.
+--------------------------------------------------------------------------------
+-- Copy of the interface declaration of Entity 'LED_DRIVER' :
+-- 
+--   port(
+--     CLK10MHz : in     std_logic;
+--     INP      : in     std_logic;
+--     OUTP     : out    std_logic;
+--     SYSRST   : in     std_logic);
+-- 
+-- EASE/HDL end ----------------------------------------------------------------
+
+architecture a0 of LED_DRIVER is
+
+signal LEDSHINE_COUNTER: std_logic_vector(20 downto 0); -- Full is about 0.2 seconds
+
+begin
+
+  process(CLK10MHz, SYSRST, INP)
+  begin
+    if (SYSRST = '1' or INP = '1') then
+      LEDSHINE_COUNTER <= "000000000000000000000";
+    elsif (CLK10MHz'event and CLK10MHz = '1') then
+      if (LEDSHINE_COUNTER /= "111111111111111111111") then
+        LEDSHINE_COUNTER <= LEDSHINE_COUNTER + "000000000000000000001";
+      else
+        LEDSHINE_COUNTER <= LEDSHINE_COUNTER; -- locks at full
+      end if;
+    end if;
+  end process;
+
+  OUTP <= '1' when (LEDSHINE_COUNTER /= "111111111111111111111") else '0';
+
+end architecture a0 ; -- of LED_DRIVER
+

hisparc.ews/design/LED_ONE_SHOT/a0/a0.vhd

@@ -1,14 +1,17 @@
 -- EASE/HDL begin --------------------------------------------------------------
--- Architecture 'a0' of 'LED_ONE_SHOT.
+-- 
+-- Architecture 'a0' of entity 'LED_ONE_SHOT'.
+-- 
 --------------------------------------------------------------------------------
--- Copy of the interface declaration of Entity 'LED_ONE_SHOT' :
+-- 
+-- Copy of the interface declaration:
 -- 
 --   port(
 --     CLK10MHz : in     std_logic;
 --     INP      : in     std_logic;
+--     OUTP     : out    std_logic;
 --     STARTUP  : in     std_logic;
---     SYSRST   : in     std_logic;
---     nOUTP    : out    std_logic);
+--     SYSRST   : in     std_logic);
 -- 
 -- EASE/HDL end ----------------------------------------------------------------
 
@@ -35,7 +38,7 @@ begin
     end if;
   end process;
 
-  nOUTP <= STARTUP or not LED_ON;
+  OUTP <= LED_ON and not STARTUP;
 
 end architecture a0 ; -- of LED_ONE_SHOT
 

hisparc.ews/design/LED_ONE_SHOT/a0/a0.vhd.bk!

@@ -0,0 +1,41 @@
+-- EASE/HDL begin --------------------------------------------------------------
+-- Architecture 'a0' of 'LED_ONE_SHOT.
+--------------------------------------------------------------------------------
+-- Copy of the interface declaration of Entity 'LED_ONE_SHOT' :
+-- 
+--   port(
+--     CLK10MHz : in     std_logic;
+--     INP      : in     std_logic;
+--     OUTP     : out    std_logic;
+--     STARTUP  : in     std_logic;
+--     SYSRST   : in     std_logic);
+-- 
+-- EASE/HDL end ----------------------------------------------------------------
+
+architecture a0 of LED_ONE_SHOT is
+
+signal LEDSHINE_COUNTER: std_logic_vector(20 downto 0); -- Full is about 0.2 seconds
+signal LED_ON: std_logic;
+
+begin
+
+  process(CLK10MHz, SYSRST, INP)
+  begin
+    if (SYSRST = '1' or INP = '1') then
+      LEDSHINE_COUNTER <= "000000000000000000000";
+      LED_ON <= '0';
+    elsif (CLK10MHz'event and CLK10MHz = '1') then
+      if (LEDSHINE_COUNTER /= "111111111111111111111") then
+        LEDSHINE_COUNTER <= LEDSHINE_COUNTER + "000000000000000000001";
+        LED_ON <= '1';
+      else
+        LEDSHINE_COUNTER <= LEDSHINE_COUNTER; -- locks at full
+        LED_ON <= '0';
+      end if;
+    end if;
+  end process;
+
+  OUTP <= LED_ON and not STARTUP;
+
+end architecture a0 ; -- of LED_ONE_SHOT
+

hisparc.ews/design/LVDS_MUX/a0/a0.vhd

@@ -1,7 +1,10 @@
 -- EASE/HDL begin --------------------------------------------------------------
--- Architecture 'a0' of 'LVDS_MUX.
+-- 
+-- Architecture 'a0' of entity 'LVDS_MUX'.
+-- 
 --------------------------------------------------------------------------------
--- Copy of the interface declaration of Entity 'LVDS_MUX' :
+-- 
+-- Copy of the interface declaration:
 -- 
 --   port(
 --     CLK10MHz        : in     std_logic;