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Jzjerry/readme.md

Hi, I'm JIANG (Jerry) Zijun

Click here to learn more about me!

✨Fancy Stuffs✨

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Code Time

Profile Views

I'm an Early 🐤

🌞 Morning                68 commits          █░░░░░░░░░░░░░░░░░░░░░░░░   04.90 % 
🌆 Daytime                731 commits         █████████████░░░░░░░░░░░░   52.67 % 
🌃 Evening                511 commits         █████████░░░░░░░░░░░░░░░░   36.82 % 
🌙 Night                  78 commits          █░░░░░░░░░░░░░░░░░░░░░░░░   05.62 % 

📅 I'm Most Productive on Monday

Monday                   289 commits         █████░░░░░░░░░░░░░░░░░░░░   20.82 % 
Tuesday                  266 commits         █████░░░░░░░░░░░░░░░░░░░░   19.16 % 
Wednesday                200 commits         ████░░░░░░░░░░░░░░░░░░░░░   14.41 % 
Thursday                 227 commits         ████░░░░░░░░░░░░░░░░░░░░░   16.35 % 
Friday                   210 commits         ████░░░░░░░░░░░░░░░░░░░░░   15.13 % 
Saturday                 101 commits         ██░░░░░░░░░░░░░░░░░░░░░░░   07.28 % 
Sunday                   95 commits          ██░░░░░░░░░░░░░░░░░░░░░░░   06.84 % 

📊 This Week I Spent My Time On

🕑︎ Time Zone: Asia/Shanghai

💬 Programming Languages: 
Python                   1 hr 38 mins        ████████████████░░░░░░░░░   62.66 % 
Markdown                 24 mins             ████░░░░░░░░░░░░░░░░░░░░░   15.92 % 
Assembly                 14 mins             ██░░░░░░░░░░░░░░░░░░░░░░░   09.38 % 
C                        5 mins              █░░░░░░░░░░░░░░░░░░░░░░░░   03.72 % 
S                        4 mins              █░░░░░░░░░░░░░░░░░░░░░░░░   03.03 % 

🔥 Editors: 
VS Code                  2 hrs 36 mins       █████████████████████████   100.00 % 

💻 Operating System: 
WSL                      1 hr 19 mins        █████████████░░░░░░░░░░░░   50.82 % 
Linux                    1 hr 17 mins        ████████████░░░░░░░░░░░░░   49.18 % 

I Mostly Code in Python

Python                   11 repos            ██████░░░░░░░░░░░░░░░░░░░   25.00 % 
C++                      7 repos             ████░░░░░░░░░░░░░░░░░░░░░   15.91 % 
Verilog                  7 repos             ████░░░░░░░░░░░░░░░░░░░░░   15.91 % 
Scala                    7 repos             ████░░░░░░░░░░░░░░░░░░░░░   15.91 % 
C                        7 repos             ████░░░░░░░░░░░░░░░░░░░░░   15.91 % 

Last Updated on 17/11/2024 18:41:36 UTC

Pinned Loading

  1. Jzjerry.github.io Jzjerry.github.io Public

    HTML 2

  2. VexRiscv VexRiscv Public

    Forked from SpinalHDL/VexRiscv

    A FPGA friendly 32 bit RISC-V CPU implementation

    Assembly 1

  3. VexiiRiscv VexiiRiscv Public

    Forked from SpinalHDL/VexiiRiscv

    Scala

  4. NodeMCU_LCD NodeMCU_LCD Public

    A simple monitor for Bilibili livers based on ESP8266 & TFT_eSPI

    C++ 2