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Use only R10
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LucasSte committed Dec 6, 2024
1 parent f602770 commit 166f893
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Showing 10 changed files with 44 additions and 63 deletions.
10 changes: 6 additions & 4 deletions llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,8 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSBFDisassembler() {

static const unsigned GPRDecoderTable[] = {
SBF::R0, SBF::R1, SBF::R2, SBF::R3, SBF::R4, SBF::R5,
SBF::R6, SBF::R7, SBF::R8, SBF::R9, SBF::R10, SBF::R11};
SBF::R6, SBF::R7, SBF::R8, SBF::R9, SBF::R10
};

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
Expand All @@ -101,12 +102,13 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,

static const unsigned GPR32DecoderTable[] = {
SBF::W0, SBF::W1, SBF::W2, SBF::W3, SBF::W4, SBF::W5,
SBF::W6, SBF::W7, SBF::W8, SBF::W9, SBF::W10, SBF::W11};
SBF::W6, SBF::W7, SBF::W8, SBF::W9, SBF::W10
};

static DecodeStatus
DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t /*Address*/,
const MCDisassembler * /*Decoder*/) {
if (RegNo > 11)
if (RegNo > 10)
return MCDisassembler::Fail;

unsigned Reg = GPR32DecoderTable[RegNo];
Expand All @@ -118,7 +120,7 @@ static DecodeStatus decodeMemoryOpValue(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
unsigned Register = (Insn >> 16) & 0xf;
if (Register > 11)
if (Register > 10)
return MCDisassembler::Fail;

Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/SBF/MCTargetDesc/SBFMCTargetDesc.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ static MCInstrInfo *createSBFMCInstrInfo() {

static MCRegisterInfo *createSBFMCRegisterInfo(const Triple &TT) {
MCRegisterInfo *X = new MCRegisterInfo();
InitSBFMCRegisterInfo(X, SBF::R11 /* RAReg doesn't exist */);
InitSBFMCRegisterInfo(X, SBF::R10 /* RAReg doesn't exist */);
return X;
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SBF/SBFFrameLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,8 @@ void adjustStackPointer(MachineFunction &MF, MachineBasicBlock &MBB,
DebugLoc Dl;
const SBFInstrInfo &TII =
*static_cast<const SBFInstrInfo *>(MF.getSubtarget().getInstrInfo());
BuildMI(MBB, MBBI, Dl, TII.get(SBF::ADD_ri), SBF::R11)
.addReg(SBF::R11)
BuildMI(MBB, MBBI, Dl, TII.get(SBF::ADD_ri), SBF::R10)
.addReg(SBF::R10)
.addImm(IsSubtract ? -NumBytes : NumBytes);
}
}
Expand Down
47 changes: 16 additions & 31 deletions llvm/lib/Target/SBF/SBFISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,8 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
// Compute derived properties from the register classes
computeRegisterProperties(STI.getRegisterInfo());

setStackPointerRegisterToSaveRestore(SBF::R11);
if (Subtarget->getHasDynamicFrames())
setStackPointerRegisterToSaveRestore(SBF::R10);

setOperationAction(ISD::BR_CC, MVT::i64, Custom);
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
Expand Down Expand Up @@ -356,7 +357,7 @@ SDValue SBFTargetLowering::LowerFormalArguments(
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
if (Ins.size() > MaxArgs) {
if (Subtarget->getEnableNewCallConvention()) {
if (Subtarget->getHasDynamicFrames()) {
// Pass args 1-5 via registers, remaining args via stack.
CCInfo.AnalyzeFormalArguments(Ins, getHasAlu32() ? CC_SBF32 : CC_SBF64);
} else {
Expand Down Expand Up @@ -412,9 +413,9 @@ SDValue SBFTargetLowering::LowerFormalArguments(
EVT LocVT = VA.getLocVT();

SDValue SDV;
if (Subtarget->getEnableNewCallConvention()) {
// In the new convention, arguments are in at the start
// of the callee frame
if (Subtarget->getHasDynamicFrames()) {
// In the new convention, arguments are in at the end of the callee
// frame.
uint64_t Size = PtrVT.getFixedSizeInBits() / 8;
int64_t Offset = -static_cast<int64_t>(VA.getLocMemOffset() + Size);
int FrameIndex =
Expand All @@ -424,14 +425,7 @@ SDValue SBFTargetLowering::LowerFormalArguments(
MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset);
SDV = DAG.getLoad(LocVT, DL, Chain, DstAddr, DstInfo);
} else {
unsigned Offset;
if (Subtarget->getHasDynamicFrames()) {
// In the old convention, the arguments are stored on
// the start of caller the frame.
Offset = VA.getLocMemOffset() + PtrVT.getFixedSizeInBits() / 8;
} else {
Offset = SBFRegisterInfo::FrameLength - VA.getLocMemOffset();
}
unsigned Offset = SBFRegisterInfo::FrameLength - VA.getLocMemOffset();

// Arguments relative to SBF::R5
unsigned reg = MF.addLiveIn(SBF::R5, &SBF::GPRRegClass);
Expand Down Expand Up @@ -483,7 +477,7 @@ SDValue SBFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
if (Outs.size() > MaxArgs) {
if (Subtarget->getEnableNewCallConvention()) {
if (Subtarget->getHasDynamicFrames()) {
// Pass args 1-5 via registers, remaining args via stack
CCInfo.AnalyzeCallOperands(Outs, getHasAlu32() ? CC_SBF32 : CC_SBF64);
} else {
Expand Down Expand Up @@ -559,33 +553,24 @@ SDValue SBFTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
SDValue DstAddr;
MachinePointerInfo DstInfo;
int FrameIndex;
int64_t Offset;
int64_t Offset = static_cast<int64_t>(VA.getLocMemOffset());
uint64_t Size = VA.getLocVT().getFixedSizeInBits() / 8;
if (Subtarget->getHasDynamicFrames()) {
// In the new call convention, arguments are stored in the callee frame
// The positive offset signals that the variable does not occupy space
// in the caller frame.
Offset = static_cast<int64_t>(VA.getLocMemOffset() +
PtrVT.getFixedSizeInBits() / 8);
if (!Subtarget->getEnableNewCallConvention())
// In the old call convention, we place argument at the start of the
// frame in a fixed stack offset.
Offset = -Offset;

FrameIndex = MF.getFrameInfo().CreateFixedObject(
VA.getLocVT().getFixedSizeInBits() / 8, Offset, false);
} else {
Offset = static_cast<int64_t>(VA.getLocMemOffset());
FrameIndex = MF.getFrameInfo().CreateFixedObject(
VA.getLocVT().getFixedSizeInBits() / 8, Offset, false);
// We must increase the offset, simply because offset zero belongs to
// the caller.
Offset += Size;
}

FrameIndex = MF.getFrameInfo().CreateFixedObject(
Size, Offset, false);
SBFFuncInfo->storeFrameIndexArgument(FrameIndex);
DstAddr = DAG.getFrameIndex(FrameIndex, PtrVT);
DstInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex, Offset);
Chain = DAG.getStore(Chain, CLI.DL, Arg, DstAddr, DstInfo);
}

if (!Subtarget->getEnableNewCallConvention()) {
if (!Subtarget->getHasDynamicFrames()) {
// Pass the current stack frame pointer via SBF::R5, gluing the
// instruction to instructions passing the first 4 arguments in
// registers below.
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/SBF/SBFInstrInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -648,7 +648,7 @@ let isBranch = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1 in {
}

// Jump and link
let isCall=1, hasDelaySlot=0, Uses = [R11],
let isCall=1, hasDelaySlot=0, Uses = [R10],
// Potentially clobbered registers
Defs = [R0, R1, R2, R3, R4, R5] in {
def JAL : CALL<"call">;
Expand Down Expand Up @@ -689,7 +689,7 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot=0, isBarrier = 1,
}

// ADJCALLSTACKDOWN/UP pseudo insns
let Defs = [R11], Uses = [R11], isCodeGenOnly = 1 in {
let Defs = [R10], Uses = [R10], isCodeGenOnly = 1 in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
"#ADJCALLSTACKDOWN $amt1 $amt2",
[(SBFcallseq_start timm:$amt1, timm:$amt2)]>;
Expand Down
24 changes: 15 additions & 9 deletions llvm/lib/Target/SBF/SBFRegisterInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,6 @@ SBFRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
BitVector SBFRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
markSuperRegs(Reserved, SBF::W10); // [W|R]10 is read only frame pointer
markSuperRegs(Reserved, SBF::W11); // [W|R]11 is pseudo stack pointer
return Reserved;
}

Expand Down Expand Up @@ -149,8 +148,10 @@ int SBFRegisterInfo::resolveInternalFrameIndex(
const MachineFrameInfo &MFI = MF.getFrameInfo();
const SBFFunctionInfo *SBFFuncInfo = MF.getInfo<SBFFunctionInfo>();
int Offset = MFI.getObjectOffset(FI);
const SBFSubtarget & SubTarget = MF.getSubtarget<SBFSubtarget>();
uint64_t StackSize = MFI.getStackSize();

if (!MF.getSubtarget<SBFSubtarget>().getHasDynamicFrames() &&
if (!SubTarget.getHasDynamicFrames() &&
SBFFuncInfo->containsFrameIndex(FI)) {
Offset = SBFRegisterInfo::FrameLength - Offset;
if (static_cast<uint64_t>(Offset) < MFI.getStackSize()) {
Expand All @@ -161,13 +162,18 @@ int SBFRegisterInfo::resolveInternalFrameIndex(
<< "The function call may cause undefined behavior "
"during execution.\n\n";
}
Offset = -Offset;
} else if (MF.getSubtarget<SBFSubtarget>().getEnableNewCallConvention() &&
SBFFuncInfo->containsFrameIndex(FI)) {
uint64_t StackSize = MFI.getStackSize();
Offset = -static_cast<int>(StackSize) - Offset;
} else if (Imm.has_value()) {
Offset += Imm.value();
return -Offset;
}

if (SubTarget.getHasDynamicFrames() &&
SBFFuncInfo->containsFrameIndex(FI)) {
return -Offset;
}

Offset += Imm.value_or(0);

if (SubTarget.getHasDynamicFrames()) {
return static_cast<int>(StackSize) + Offset;
}

return Offset;
Expand Down
4 changes: 1 addition & 3 deletions llvm/lib/Target/SBF/SBFRegisterInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ class Ri<bits<16> Enc, string n, list<Register> subregs>
let SubRegIndices = [sub_32];
}

foreach I = 0-11 in {
foreach I = 0-10 in {
// 32-bit Integer (alias to low part of 64-bit register).
def W#I : Wi<I, "w"#I>, DwarfRegNum<[I]>;
// 64-bit Integer registers
Expand All @@ -39,13 +39,11 @@ foreach I = 0-11 in {
def GPR32 : RegisterClass<"SBF", [i32], 64, (add
(sequence "W%u", 1, 9),
W0, // Return value
W11, // Stack Ptr
W10 // Frame Ptr
)>;

def GPR : RegisterClass<"SBF", [i64], 64, (add
(sequence "R%u", 1, 9),
R0, // Return value
R11, // Stack Ptr
R10 // Frame Ptr
)>;
1 change: 0 additions & 1 deletion llvm/lib/Target/SBF/SBFSubtarget.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,6 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) {
NoLddw = false;
CallxRegSrc = false;
HasPqrClass = false;
NewCallConvention = false;
HasStoreImm = false;
}

Expand Down
6 changes: 0 additions & 6 deletions llvm/lib/Target/SBF/SBFSubtarget.h
Original file line number Diff line number Diff line change
Expand Up @@ -74,9 +74,6 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
// Whether we have the PQR instruction class
bool HasPqrClass;

// Whether to use the new call convention in SBFv2
bool NewCallConvention;

// Whether we have store imm instructions
bool HasStoreImm;

Expand Down Expand Up @@ -104,9 +101,6 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
bool getNoLddw() const { return NoLddw; }
bool getCallXRegSrc() const { return CallxRegSrc; }
bool getHasPqrClass() const { return HasPqrClass; }
bool getEnableNewCallConvention() const {
return HasDynamicFrames && NewCallConvention;
}
bool getHasStoreImm() const { return HasStoreImm; }
bool getHasExplicitSignExt() const { return HasExplicitSignExt; }
const SBFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
Expand Down
5 changes: 1 addition & 4 deletions llvm/lib/Target/SBF/SBFTargetFeatures.td
Original file line number Diff line number Diff line change
Expand Up @@ -40,9 +40,6 @@ def FeatureCallxRegSrc : SubtargetFeature<"callx-reg-src", "CallxRegSrc", "true"
def FeaturePqrInstr : SubtargetFeature<"pqr-instr", "HasPqrClass", "true",
"Enable the PQR instruction class">;

def FeatureCallConv : SubtargetFeature<"new-call-conv", "NewCallConvention", "true",
"Enable new call convetion for SBFv2">;

def FeatureStoreImm : SubtargetFeature<"store-imm", "HasStoreImm", "true",
"Enable store imm instructions">;

Expand All @@ -58,4 +55,4 @@ def : Proc<"v2", []>;
def : Proc<"v3", [ALU32]>;
def : Proc<"sbfv2", [FeatureDynamicFrames, FeatureRelocAbs64, FeatureStaticSyscalls,
FeatureDisableNeg, FeatureReverseSubImm, FeatureDisableLddw, FeatureCallxRegSrc,
FeaturePqrInstr, FeatureCallConv, FeatureExplicitSext]>;
FeaturePqrInstr, FeatureExplicitSext]>;

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