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Fixed tests
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@LucasSte
LucasSte committed Dec 13, 2024
1 parent 2bd1d02 commit 27db3d8
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Showing 5 changed files with 114 additions and 103 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/Target/SBF/SBFInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1029,7 +1029,7 @@ let isCodeGenOnly = 1 in {
[]>;
def AND_32_zero_ext : MATH_RI<SBF_ALU, SBF_AND,
(outs GPR:$dst),
(ins i64imm:$imm),
(ins GPR:$src, i64imm:$imm),
"and32 $dst, $imm",
[]>;
}
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152 changes: 100 additions & 52 deletions llvm/lib/Target/SBF/SBFMIPeephole.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -56,8 +56,9 @@ struct SBFMIPeephole : public MachineFunctionPass {
bool isInsnFrom32Def(MachineInstr *DefInsn);
bool isPhiFrom32Def(MachineInstr *MovMI);
bool isMovFrom32Def(MachineInstr *MovMI);
bool simplifySext();
bool simplifyZext();
bool eliminateZExt();
bool simplifySExt();
bool simplifyZExt();

std::set<MachineInstr *> PhiInsns;

Expand All @@ -70,7 +71,7 @@ struct SBFMIPeephole : public MachineFunctionPass {

initialize(MF);

return simplifySext() || simplifyZext();
return simplifySExt() || simplifyZExt() || eliminateZExt();
}
};

Expand Down Expand Up @@ -167,59 +168,60 @@ bool SBFMIPeephole::isMovFrom32Def(MachineInstr *MovMI)
return true;
}

bool SBFMIPeephole::simplifyZext() {
bool SBFMIPeephole::simplifyZExt() {
MachineInstr* ToErase = nullptr;
bool Eliminated = false;
// for (MachineBasicBlock &MBB : *MF) {
// for (MachineInstr &MI : MBB) {
//
// // If the previous instruction was marked for elimination, remove it now.
// if (ToErase) {
// ToErase->eraseFromParent();
// ToErase = nullptr;
// }
//
// // Eliminate the 32-bit to 64-bit sign extension sequence when we are
// // emulating 32-bit arithmetics with ALU64 instructions.
// //
// // MOV64 rB, rA
// // SLL_ri rB, rB, 32
// // SRR_ri rB, rB, 32
// if (MI.getOpcode() == SBF::SRL_ri &&
// MI.getOperand(2).getImm() == 32) {
// Register DstReg = MI.getOperand(0).getReg();
// Register ShfReg = MI.getOperand(1).getReg();
// MachineInstr *SllMI = MRI->getVRegDef(ShfReg);
//
// LLVM_DEBUG(dbgs() << "Starting SRA_ri found:");
// LLVM_DEBUG(MI.dump());
// if (!SllMI ||
// SllMI->isPHI() ||
// SllMI->getOpcode() != SBF::SLL_ri ||
// SllMI->getOperand(2).getImm() != 32)
// continue;
// LLVM_DEBUG(dbgs() << " SLL found:");
// LLVM_DEBUG(SllMI->dump());
//
// MachineInstr *PrevMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
// if (!PrevMI ||
// PrevMI->isPHI())
// continue;
//
// BuildMI(MBB, MI, MI.getDebugLoc(),
// TII->get(SBF::AND_32_zero_ext), DstReg)
// .addImm(0xffffffff);
//
// SllMI->eraseFromParent();
// ToErase = &MI;
// Eliminated = true;
// }
// }
// }
for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {

// If the previous instruction was marked for elimination, remove it now.
if (ToErase) {
ToErase->eraseFromParent();
ToErase = nullptr;
}

// Eliminate the 32-bit to 64-bit sign extension sequence when we are
// emulating 32-bit arithmetics with ALU64 instructions.
//
// MOV64 rB, rA
// SLL_ri rB, rB, 32
// SRR_ri rB, rB, 32
if (MI.getOpcode() == SBF::SRL_ri &&
MI.getOperand(2).getImm() == 32) {
Register DstReg = MI.getOperand(0).getReg();
Register ShfReg = MI.getOperand(1).getReg();
MachineInstr *SllMI = MRI->getVRegDef(ShfReg);

LLVM_DEBUG(dbgs() << "Starting SRA_ri found:");
LLVM_DEBUG(MI.dump());
if (!SllMI ||
SllMI->isPHI() ||
SllMI->getOpcode() != SBF::SLL_ri ||
SllMI->getOperand(2).getImm() != 32)
continue;
LLVM_DEBUG(dbgs() << " SLL found:");
LLVM_DEBUG(SllMI->dump());

MachineInstr *PrevMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
if (!PrevMI ||
PrevMI->isPHI())
continue;

Register SrcReg = PrevMI->getOperand(0).getReg();
BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(SBF::AND_32_zero_ext), DstReg)
.addReg(SrcReg).addImm(0xffffffff);

SllMI->eraseFromParent();
ToErase = &MI;
Eliminated = true;
}
}
}
return Eliminated;
}

bool SBFMIPeephole::simplifySext() {
bool SBFMIPeephole::simplifySExt() {
MachineInstr* ToErase = nullptr;
bool Eliminated = false;
for (MachineBasicBlock &MBB : *MF) {
Expand Down Expand Up @@ -260,7 +262,13 @@ bool SBFMIPeephole::simplifySext() {
MovMI->getOpcode() != SBF::MOV_rr))
continue;

Register SubReg = MovMI->getOperand(0).getReg();
if (!isMovFrom32Def(MovMI)) {
LLVM_DEBUG(dbgs()
<< " One SExt elim sequence failed qualifying elim.\n");
continue;
}

Register SubReg = MovMI->getOperand(1).getReg();
BuildMI(MBB, MI, MI.getDebugLoc(),
TII->get(SBF::MOV_64_sign_ext), DstReg)
.addReg(SubReg);
Expand All @@ -275,6 +283,46 @@ bool SBFMIPeephole::simplifySext() {
return Eliminated;
}

bool SBFMIPeephole::eliminateZExt() {
MachineInstr* ToErase = nullptr;
bool Eliminated = false;

for (MachineBasicBlock &MBB : *MF) {
for (MachineInstr &MI : MBB) {
// If the previous instruction was marked for elimination, remove it now.
if (ToErase) {
ToErase->eraseFromParent();
ToErase = nullptr;
}

if (MI.getOpcode() != SBF::MOV_32_64_no_sext)
continue;

// Eliminate MOV_32_64 if possible.
// MOV_32_64 rA, wB
LLVM_DEBUG(dbgs() << "Candidate MOV_32_64_no_sext instruction:");
LLVM_DEBUG(MI.dump());

if (!isMovFrom32Def(&MI))
continue;

LLVM_DEBUG(dbgs() << "Removing the MOV_32_64_no_sext instruction\n");

Register dst = MI.getOperand(0).getReg();
Register src = MI.getOperand(1).getReg();

// Build a SUBREG_TO_REG instruction.
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(SBF::SUBREG_TO_REG), dst)
.addImm(0).addReg(src).addImm(SBF::sub_32);

ToErase = &MI;
Eliminated = true;
}
}

return Eliminated;
}

} // end default namespace

INITIALIZE_PASS(SBFMIPeephole, DEBUG_TYPE,
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/SBF/atomics_sbf.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -67,9 +67,9 @@ entry:

; CHECK-LABEL: test_cas_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, w0
; CHECK-NOT: mov64 r4, w0
; CHECK: mov64 r2, w2
; CHECK: jeq r4, r2,
; CHECK: jeq r0, r2,
; CHECK: mov64 w3, w0
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_cas_32(i32* nocapture %p, i32 %old, i32 %new) local_unnamed_addr {
Expand Down Expand Up @@ -236,9 +236,9 @@ entry:
; CHECK-LABEL: test_umin_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, w2
; CHECK: mov64 r5, w0
; CHECK-NOT: mov64 r5, w0
; CHECK: mov64 w3, w0
; CHECK: jgt r4, r5,
; CHECK: jgt r4, r0,
; CHECK: mov64 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_umin_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand All @@ -261,10 +261,10 @@ entry:

; CHECK-LABEL: test_umax_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, w0
; CHECK: mov64 r5, w2
; CHECK-NOT: mov64 r4, w0
; CHECK: mov64 r4, w2
; CHECK: mov64 w3, w0
; CHECK: jgt r4, r5
; CHECK: jgt r0, r4
; CHECK: mov64 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_umax_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand Down Expand Up @@ -330,9 +330,9 @@ entry:

; CHECK-LABEL: test_weak_cas_32
; CHECK: ldxw w4, [r1 + 0]
; CHECK: mov64 r5, w4
; CHECK-NOT: mov64 r5, w4
; CHECK: mov64 r2, w2
; CHECK: jeq r5, r2,
; CHECK: jeq r4, r2,
; CHECK: stxw [r1 + 0], w3
define dso_local void @test_weak_cas_32(i32* nocapture %p, i32 %old, i32 %new) local_unnamed_addr {
entry:
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8 changes: 4 additions & 4 deletions llvm/test/CodeGen/SBF/objdump_cond_op.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -47,12 +47,12 @@ define i32 @test(i32, i32) local_unnamed_addr #0 {
br label %13

; CHECK-LABEL: <LBB0_2>:
; CHECK: mov32 r2, 0x0
; CHECK: hor64 r2, 0x0
; CHECK: ldxw r0, [r2 + 0x0]
; CHECK: mov32 r3, 0x0
; CHECK: hor64 r3, 0x0
; CHECK: ldxw r0, [r3 + 0x0]
; CHECK-NOT: lsh64 r2, 0x20
; CHECK-NOT: rsh64 r2, 0x20
; CHECK: and32 r2, -0x1
; CHECK: and32 w2, -0x1
; CHECK: jeq r1, r2, +0x4 <LBB0_5>
; CHECK: lsh64 r0, 0x2

Expand Down
37 changes: 0 additions & 37 deletions llvm/test/CodeGen/SBF/objdump_cond_op.s
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