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[SOL] Remove SBF_JMP32 instruction class (anza-xyz#80)
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* Remove SBF_JMP32 class
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@LucasSte
LucasSte committed Jun 28, 2024
1 parent e7a18d9 commit 492df33
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Showing 16 changed files with 51 additions and 255 deletions.
1 change: 0 additions & 1 deletion llvm/lib/Target/SBF/Disassembler/SBFDisassembler.cpp
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Expand Up @@ -40,7 +40,6 @@ class SBFDisassembler : public MCDisassembler {
SBF_STX = 0x3,
SBF_ALU = 0x4,
SBF_JMP = 0x5,
SBF_JMP32 = 0x6,
SBF_ALU64 = 0x7
};

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19 changes: 7 additions & 12 deletions llvm/lib/Target/SBF/SBFISelLowering.cpp
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Expand Up @@ -150,8 +150,7 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,

if (STI.getHasAlu32()) {
setOperationAction(ISD::BSWAP, MVT::i32, Promote);
setOperationAction(ISD::BR_CC, MVT::i32,
STI.getHasJmp32() ? Custom : Promote);
setOperationAction(ISD::BR_CC, MVT::i32, Promote);
}

if (Subtarget->isSolana()) {
Expand Down Expand Up @@ -219,7 +218,6 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,

// CPU/Feature control
HasAlu32 = STI.getHasAlu32();
HasJmp32 = STI.getHasJmp32();
HasJmpExt = STI.getHasJmpExt();
SBFRegisterInfo::FrameLength = STI.isSolana() ? 4096 : 512;
}
Expand Down Expand Up @@ -800,7 +798,7 @@ SDValue SBFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
NegateCC(LHS, RHS, CC);

return DAG.getNode(SBFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
DAG.getConstant(CC, DL, LHS.getValueType()), Dest);
DAG.getConstant(CC, DL, MVT::i64), Dest);
}

SDValue SBFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
Expand Down Expand Up @@ -1091,12 +1089,9 @@ SBFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
int CC = MI.getOperand(3).getImm();
int NewCC;
switch (CC) {
#define SET_NEWCC(X, Y) \
case ISD::X: \
if (is32BitCmp && HasJmp32) \
NewCC = isSelectRROp ? SBF::Y##_rr_32 : SBF::Y##_ri_32; \
else \
NewCC = isSelectRROp ? SBF::Y##_rr : SBF::Y##_ri; \
#define SET_NEWCC(X, Y) \
case ISD::X: \
NewCC = isSelectRROp ? SBF::Y##_rr : SBF::Y##_ri; \
break
SET_NEWCC(SETGT, JSGT);
SET_NEWCC(SETUGT, JUGT);
Expand Down Expand Up @@ -1125,13 +1120,13 @@ SBFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
//
// We simply do extension for all situations in this method, but we will
// try to remove those unnecessary in SBFMIPeephole pass.
if (is32BitCmp && !HasJmp32)
if (is32BitCmp)
LHS = EmitSubregExt(MI, BB, LHS, isSignedCmp);

if (isSelectRROp) {
Register RHS = MI.getOperand(2).getReg();

if (is32BitCmp && !HasJmp32)
if (is32BitCmp)
RHS = EmitSubregExt(MI, BB, RHS, isSignedCmp);

BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB);
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2 changes: 0 additions & 2 deletions llvm/lib/Target/SBF/SBFISelLowering.h
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Expand Up @@ -63,7 +63,6 @@ class SBFTargetLowering : public TargetLowering {
MachineBasicBlock *BB) const override;

bool getHasAlu32() const { return HasAlu32; }
bool getHasJmp32() const { return HasJmp32; }
bool getHasJmpExt() const { return HasJmpExt; }

EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
Expand All @@ -77,7 +76,6 @@ class SBFTargetLowering : public TargetLowering {
private:
// Control Instruction Selection Features
bool HasAlu32;
bool HasJmp32;
bool HasJmpExt;

SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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1 change: 0 additions & 1 deletion llvm/lib/Target/SBF/SBFInstrFormats.td
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Expand Up @@ -16,7 +16,6 @@ def SBF_ST : SBFOpClass<0x2>;
def SBF_STX : SBFOpClass<0x3>;
def SBF_ALU : SBFOpClass<0x4>;
def SBF_JMP : SBFOpClass<0x5>;
def SBF_JMP32 : SBFOpClass<0x6>;
def SBF_ALU64 : SBFOpClass<0x7>;

class SBFSrcType<bits<1> val> {
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76 changes: 11 additions & 65 deletions llvm/lib/Target/SBF/SBFInstrInfo.td
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Expand Up @@ -126,26 +126,6 @@ def SBF_CC_LTU : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETULT);}]>;
def SBF_CC_LEU : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETULE);}]>;
def SBF_CC_EQ_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETEQ);}]>;
def SBF_CC_NE_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETNE);}]>;
def SBF_CC_GE_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETGE);}]>;
def SBF_CC_GT_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETGT);}]>;
def SBF_CC_GTU_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETUGT);}]>;
def SBF_CC_GEU_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETUGE);}]>;
def SBF_CC_LE_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETLE);}]>;
def SBF_CC_LT_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETLT);}]>;
def SBF_CC_LTU_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETULT);}]>;
def SBF_CC_LEU_32 : PatLeaf<(i32 imm),
[{return (N->getZExtValue() == ISD::SETULE);}]>;

// For arithmetic and jump instructions the 8-bit 'code'
// field is divided into three parts:
Expand Down Expand Up @@ -211,57 +191,23 @@ class JMP_RI<SBFJumpOp Opc, string Mnemonic, PatLeaf Cond>
let SBFClass = SBF_JMP;
}

class JMP_RR_32<SBFJumpOp Opc, string Mnemonic, PatLeaf Cond>
: TYPE_ALU_JMP<Opc.Value, SBF_X.Value,
(outs),
(ins GPR32:$dst, GPR32:$src, brtarget:$BrDst),
Mnemonic # " $dst, $src, $BrDst",
[(SBFbrcc i32:$dst, i32:$src, Cond, bb:$BrDst)]> {
bits<4> dst;
bits<4> src;
bits<16> BrDst;

let Inst{55-52} = src;
let Inst{51-48} = dst;
let Inst{47-32} = BrDst;
let SBFClass = SBF_JMP32;
}

class JMP_RI_32<SBFJumpOp Opc, string Mnemonic, PatLeaf Cond>
: TYPE_ALU_JMP<Opc.Value, SBF_K.Value,
(outs),
(ins GPR32:$dst, i32imm:$imm, brtarget:$BrDst),
Mnemonic # " $dst, $imm, $BrDst",
[(SBFbrcc i32:$dst, i32immSExt32:$imm, Cond, bb:$BrDst)]> {
bits<4> dst;
bits<16> BrDst;
bits<32> imm;

let Inst{51-48} = dst;
let Inst{47-32} = BrDst;
let Inst{31-0} = imm;
let SBFClass = SBF_JMP32;
}

multiclass J<SBFJumpOp Opc, string Mnemonic, PatLeaf Cond, PatLeaf Cond32> {
multiclass J<SBFJumpOp Opc, string Mnemonic, PatLeaf Cond> {
def _rr : JMP_RR<Opc, Mnemonic, Cond>;
def _ri : JMP_RI<Opc, Mnemonic, Cond>;
def _rr_32 : JMP_RR_32<Opc, Mnemonic, Cond32>;
def _ri_32 : JMP_RI_32<Opc, Mnemonic, Cond32>;
}

let isBranch = 1, isTerminator = 1, hasDelaySlot=0 in {
// cmp+goto instructions
defm JEQ : J<SBF_JEQ, "jeq", SBF_CC_EQ, SBF_CC_EQ_32>;
defm JUGT : J<SBF_JGT, "jgt", SBF_CC_GTU, SBF_CC_GTU_32>;
defm JUGE : J<SBF_JGE, "jge", SBF_CC_GEU, SBF_CC_GEU_32>;
defm JNE : J<SBF_JNE, "jne", SBF_CC_NE, SBF_CC_NE_32>;
defm JSGT : J<SBF_JSGT, "jsgt", SBF_CC_GT, SBF_CC_GT_32>;
defm JSGE : J<SBF_JSGE, "jsge", SBF_CC_GE, SBF_CC_GE_32>;
defm JULT : J<SBF_JLT, "jlt", SBF_CC_LTU, SBF_CC_LTU_32>;
defm JULE : J<SBF_JLE, "jle", SBF_CC_LEU, SBF_CC_LEU_32>;
defm JSLT : J<SBF_JSLT, "jslt", SBF_CC_LT, SBF_CC_LT_32>;
defm JSLE : J<SBF_JSLE, "jsle", SBF_CC_LE, SBF_CC_LE_32>;
defm JEQ : J<SBF_JEQ, "jeq", SBF_CC_EQ>;
defm JUGT : J<SBF_JGT, "jgt", SBF_CC_GTU>;
defm JUGE : J<SBF_JGE, "jge", SBF_CC_GEU>;
defm JNE : J<SBF_JNE, "jne", SBF_CC_NE>;
defm JSGT : J<SBF_JSGT, "jsgt", SBF_CC_GT>;
defm JSGE : J<SBF_JSGE, "jsge", SBF_CC_GE>;
defm JULT : J<SBF_JLT, "jlt", SBF_CC_LTU>;
defm JULE : J<SBF_JLE, "jle", SBF_CC_LEU>;
defm JSLT : J<SBF_JSLT, "jslt", SBF_CC_LT>;
defm JSLE : J<SBF_JSLE, "jsle", SBF_CC_LE>;
}

// ALU instructions
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2 changes: 0 additions & 2 deletions llvm/lib/Target/SBF/SBFSubtarget.cpp
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Expand Up @@ -37,7 +37,6 @@ void SBFSubtarget::initializeEnvironment(const Triple &TT) {
assert(TT.getArch() == Triple::sbf && "expected Triple::sbf");
IsSolana = true;
HasJmpExt = false;
HasJmp32 = false;
HasAlu32 = false;
HasSdiv = false;
UseDwarfRIS = false;
Expand Down Expand Up @@ -66,7 +65,6 @@ void SBFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {

if (CPU == "v3") {
HasJmpExt = true;
HasJmp32 = true;
HasAlu32 = true;
}

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5 changes: 0 additions & 5 deletions llvm/lib/Target/SBF/SBFSubtarget.h
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Expand Up @@ -50,10 +50,6 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
// whether the cpu supports jmp ext
bool HasJmpExt;

// whether the cpu supports jmp32 ext.
// NOTE: jmp32 is not enabled when alu32 enabled.
bool HasJmp32;

// whether the cpu supports alu32 instructions.
bool HasAlu32;

Expand Down Expand Up @@ -99,7 +95,6 @@ class SBFSubtarget : public SBFGenSubtargetInfo {
void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
bool isSolana() const { return IsSolana; }
bool getHasJmpExt() const { return HasJmpExt; }
bool getHasJmp32() const { return HasJmp32; }
bool getHasAlu32() const { return HasAlu32; }
bool getHasDynamicFrames() const { return HasDynamicFrames; }
bool getHasSdiv() const { return HasSdiv; }
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SBF/adjust-opt-icmp3.ll
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Expand Up @@ -41,7 +41,7 @@ return: ; preds = %if.end, %if.then

; CHECK-LABEL: test1
; CHECK-V1: jgt r[[#]], r[[#]],
; CHECK-V3: jlt w[[#]], 4,
; CHECK-V3: jlt r[[#]], 4,

; Function Attrs: nounwind
define dso_local i32 @test2(i64 %a) #0 {
Expand Down Expand Up @@ -69,7 +69,7 @@ return: ; preds = %if.end, %if.then

; CHECK-LABEL: test2
; CHECK-V1: jgt r[[#]], r[[#]],
; CHECK-V3: jlt w[[#]], 4,
; CHECK-V3: jlt r[[#]], 4,

attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SBF/adjust-opt-icmp4.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ return: ; preds = %if.end, %if.then

; CHECK-LABEL: test1
; CHECK-V1: jgt r[[#]], 3,
; CHECK-V3: jgt w[[#]], 3,
; CHECK-V3: jgt r[[#]], 3,

; Function Attrs: nounwind
define dso_local i32 @test2(i64 %a) #0 {
Expand Down Expand Up @@ -69,7 +69,7 @@ return: ; preds = %if.end, %if.then

; CHECK-LABEL: test2
; CHECK-V1: jgt r[[#]], 3,
; CHECK-V3: jgt w[[#]], 3,
; CHECK-V3: jgt r[[#]], 3,

attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }

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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SBF/adjust-opt-icmp5.ll
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Expand Up @@ -49,8 +49,8 @@ return: ; preds = %if.end, %if.then
; CHECK-LABEL: test
; CHECK-V1: jsgt r[[#]], r[[#]],
; CHECK-V1: jsgt r[[#]], 6,
; CHECK-V3: jslt w[[#]], 1,
; CHECK-V3: jsgt w[[#]], 6,
; CHECK-V3: jslt r[[#]], 1,
; CHECK-V3: jsgt r[[#]], 6,

declare dso_local i32 @bar(i32 noundef) #1

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/SBF/adjust-opt-icmp6.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -49,8 +49,8 @@ return: ; preds = %if.end, %if.then
; CHECK-LABEL: test
; CHECK-V1: jgt r[[#]], r[[#]],
; CHECK-V1: jgt r[[#]], 6,
; CHECK-V3: jlt w[[#]], 2,
; CHECK-V3: jgt w[[#]], 6,
; CHECK-V3: jlt r[[#]], 2,
; CHECK-V3: jgt r[[#]], 6,

declare dso_local i32 @bar(i32 noundef) #1

Expand Down
24 changes: 19 additions & 5 deletions llvm/test/CodeGen/SBF/atomics_sbf.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ entry:

; CHECK-LABEL: test_cas_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: jeq w0, w2,
; CHECK: jeq r0, r2,
; CHECK: mov32 w3, w0
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_cas_32(i32* nocapture %p, i32 %old, i32 %new) local_unnamed_addr {
Expand Down Expand Up @@ -181,8 +181,14 @@ entry:

; CHECK-LABEL: test_min_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, r0
; CHECK: lsh64 r4, 32
; CHECK: arsh64 r4, 32
; CHECK: mov32 r5, w2
; CHECK: lsh64 r5, 32
; CHECK: arsh64 r5, 32
; CHECK: mov32 w3, w0
; CHECK: jslt w0, w2,
; CHECK: jslt r4, r5, LBB16_2
; CHECK: mov32 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_min_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand All @@ -205,8 +211,14 @@ entry:

; CHECK-LABEL: test_max_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov64 r4, r0
; CHECK: lsh64 r4, 32
; CHECK: arsh64 r4, 32
; CHECK: mov32 r5, w2
; CHECK: lsh64 r5, 32
; CHECK: arsh64 r5, 32
; CHECK: mov32 w3, w0
; CHECK: jsgt w0, w2,
; CHECK: jsgt r4, r5, LBB18_2
; CHECK: mov32 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_max_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand All @@ -229,8 +241,9 @@ entry:

; CHECK-LABEL: test_umin_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov32 r4, w2
; CHECK: mov32 w3, w0
; CHECK: jlt w0, w2,
; CHECK: jlt r0, r4,
; CHECK: mov32 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_umin_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand All @@ -253,8 +266,9 @@ entry:

; CHECK-LABEL: test_umax_32
; CHECK: ldxw w0, [r1 + 0]
; CHECK: mov32 r4, w2
; CHECK: mov32 w3, w0
; CHECK: jgt w0, w2,
; CHECK: jgt r0, r4,
; CHECK: mov32 w3, w2
; CHECK: stxw [r1 + 0], w3
define dso_local i32 @test_umax_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
Expand Down
9 changes: 6 additions & 3 deletions llvm/test/CodeGen/SBF/loop-exit-cond.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -49,9 +49,12 @@ for.cond: ; preds = %for.inc, %if.then
%cmp1 = icmp slt i32 %2, %3
br i1 %cmp1, label %for.body, label %for.cond.cleanup

; CHECK: mov32 w[[LEN:[0-9]+]], w1
; CHECK: add32 w[[IDX:[0-9]+]], 1
; CHECK-NEXT: jslt w[[IDX]], w[[LEN]],
; CHECK: mov32 r[[LEN:[0-9]+]], w1
; CHECK: add32 w[[IDX32:[0-9]+]], 1
; CHECK: mov64 r[[IDX:[0-9]+]], r[[IDX32:[0-9]+]]
; CHECK: lsh64 r[[IDX:[0-9]+]], 32
; CHECK: arsh64 r[[IDX:[0-9]+]], 32
; CHECK-NEXT: jslt r[[IDX]], r[[LEN]],

for.cond.cleanup: ; preds = %for.cond
%4 = bitcast i32* %i to i8*
Expand Down
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