[SOL] Enable mod instruction (anza-xyz#87)

LucasSte · Feb 23, 2024 · afc2d3d · afc2d3d
1 parent 9003b43
commit afc2d3d
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Showing 8 changed files with 81 additions and 11 deletions.
diff --git a/llvm/lib/Target/SBF/SBFISelLowering.cpp b/llvm/lib/Target/SBF/SBFISelLowering.cpp
@@ -123,7 +123,6 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
     if (Subtarget->isSolana() && !STI.getHasPqrClass()) {
       setOperationAction(ISD::SDIV, VT, Expand);
       setOperationAction(ISD::SREM, VT, Expand);
-      setOperationAction(ISD::UREM, VT, Expand);
       setOperationAction(ISD::MULHU, VT, Expand);
       setOperationAction(ISD::MULHS, VT, Expand);
     }

diff --git a/llvm/lib/Target/SBF/SBFInstrFormats.td b/llvm/lib/Target/SBF/SBFInstrFormats.td
@@ -39,6 +39,7 @@ def SBF_AND  : SBFArithOp<0x5>;
 def SBF_LSH  : SBFArithOp<0x6>;
 def SBF_RSH  : SBFArithOp<0x7>;
 def SBF_NEG  : SBFArithOp<0x8>;
+def SBF_MOD  : SBFArithOp<0x9>;
 def SBF_XOR  : SBFArithOp<0xa>;
 def SBF_MOV  : SBFArithOp<0xb>;
 def SBF_ARSH : SBFArithOp<0xc>;

diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.td b/llvm/lib/Target/SBF/SBFInstrInfo.td
@@ -324,6 +324,7 @@ let Constraints = "$dst = $src2" in {
     let Predicates = [SBFNoPqrInstr] in {
         defm MUL : ALU<SBF_MUL, "mul", mul>;
         defm DIV : ALU<SBF_DIV, "div", udiv>;
+        defm MOD : ALU<SBF_MOD, "mod", urem>;
     }
 
     let Predicates = [SBFPqrInstr] in {

diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll
@@ -51,6 +51,16 @@
 ;   return a / 0xf;
 ; }
 ;
+; unsigned rem(unsigned a, unsigned b)
+; {
+;   return a % b;
+; }
+;
+; unsigned rem_i(unsigned a)
+; {
+;   return a % 0xf;
+; }
+;
 ; int or(int a, int b)
 ; {
 ;   return a | b;
@@ -194,6 +204,22 @@ entry:
   ret i32 %div
 }
 
+; Function Attrs: norecurse nounwind readnone
+define dso_local i32 @rem(i32 %a, i32 %b) local_unnamed_addr #0 {
+entry:
+  %rem = urem i32 %a, %b
+; CHECK: mod32 w{{[0-9]+}}, w{{[0-9]+}}
+  ret i32 %rem
+}
+
+; Function Attrs: norecurse nounwind readnone
+define dso_local i32 @rem_i(i32 %a) local_unnamed_addr #0 {
+entry:
+  %rem = urem i32 %a, 15
+; CHECK: mod32 w{{[0-9]+}}, 15
+  ret i32 %rem
+}
+
 ; Function Attrs: norecurse nounwind readnone
 define dso_local i32 @or(i32 %a, i32 %b) local_unnamed_addr #0 {
 entry:

diff --git a/llvm/test/CodeGen/SBF/mod-64.ll b/llvm/test/CodeGen/SBF/mod-64.ll
@@ -0,0 +1,17 @@
+; RUN: llc -O2 -march=sbf < %s | FileCheck %s
+
+; Function Attrs: norecurse nounwind readnone
+define dso_local i64 @rem(i64 %a, i64 %b) local_unnamed_addr #0 {
+entry:
+  %rem = urem i64 %a, %b
+; CHECK: mod64 r{{[0-9]+}}, r{{[0-9]+}}
+  ret i64 %rem
+}
+
+; Function Attrs: norecurse nounwind readnone
+define dso_local i64 @rem_i(i64 %a) local_unnamed_addr #0 {
+entry:
+  %rem = urem i64 %a, 15
+; CHECK: mod64 r{{[0-9]+}}, 15
+  ret i64 %rem
+}
diff --git a/llvm/test/CodeGen/SBF/pqr-class.ll b/llvm/test/CodeGen/SBF/pqr-class.ll
@@ -16,15 +16,13 @@ entry:
 ; CHECK-v2: lmul64 r{{[0-9]+}}, r2
 ; CHECK-V2: lmul64 r{{[0-9]+}}, 7
 
+; CHECK-v1: mod64 r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-v1: div64 r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK-v1: mul64 r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK-v1: sub64 r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-v1: add64 r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK-v1: div64 r{{[0-9]+}}, 17
-; CHECK-v1: mul64 r{{[0-9]+}}, 17
 ; CHECK-v1: mov64 r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK-v1: sub64 r{{[0-9]+}}, r{{[0-9]+}}
+; CHECK-v1: mod64 r{{[0-9]+}}, 17
 ; CHECK-v1: div64 r{{[0-9]+}}, 7
+; CHECK-v1: add64 r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-v1: mul64 r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-v1: mul64 r{{[0-9]+}}, 7
 
@@ -79,14 +77,11 @@ entry:
 ; CHECK-v2: lmul32 w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK-v2: lmul32 w{{[0-9]+}}, 7
 
+; CHECK-v1: mod32 w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK-v1: div32 w{{[0-9]+}}, w{{[0-9]+}}
-; CHECK-v1: mul32 w{{[0-9]+}}, w{{[0-9]+}}
-; CHECK-v1: sub32 w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}}
-; CHECK-v1: div32 w{{[0-9]+}}, 17
-; CHECK-v1: mul32 w{{[0-9]+}}, 17
 ; CHECK-v1: mov32 w{{[0-9]+}}, w{{[0-9]+}}
-; CHECK-v1: sub32 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-v1: mod32 w{{[0-9]+}}, 17
 ; CHECK-v1: div32 w{{[0-9]+}}, 7
 ; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK-v1: mul32 w{{[0-9]+}}, w{{[0-9]+}}

diff --git a/llvm/test/MC/Disassembler/SBF/sbf-alu.txt b/llvm/test/MC/Disassembler/SBF/sbf-alu.txt
@@ -241,3 +241,17 @@
 0xdc,0x00,0x00,0x00,0x10,0x00,0x00,0x00
 0xdc,0x01,0x00,0x00,0x20,0x00,0x00,0x00
 0xdc,0x02,0x00,0x00,0x40,0x00,0x00,0x00
+
+
+# CHECK-NEW: mod64 r3, r1
+0x9f,0x13,0x00,0x00,0x00,0x00,0x00,0x00
+
+# CHECK-NEW: mod64 r3, 123
+0x97,0x03,0x00,0x00,0x7b,0x00,0x00,0x00
+
+# CHECK-NEW: mod32 w6, w2
+0x9c,0x26,0x00,0x00,0x00,0x00,0x00,0x00
+
+# CHECK-NEW: mod32 w5, -12
+0x94,0x05,0x00,0x00,0x85,0xff,0xff,0xff
+
diff --git a/llvm/test/MC/SBF/sbf-alu.s b/llvm/test/MC/SBF/sbf-alu.s
@@ -318,3 +318,20 @@ mov32 w5, -123
 be16 r0
 be32 r1
 be64 r2
+
+
+# CHECK-OBJ-NEW: mod64 r3, r1
+# CHECK-ASM-NEW: encoding: [0x9f,0x13,0x00,0x00,0x00,0x00,0x00,0x00]
+mod64 r3, r1
+
+# CHECK-OBJ-NEW: mod64 r3, 0x7b
+# CHECK-ASM-NEW: encoding: [0x97,0x03,0x00,0x00,0x7b,0x00,0x00,0x00]
+mod64 r3, 123
+
+# CHECK-OBJ-NEW: mod32 w6, w2
+# CHECK-ASM-NEW: encoding: [0x9c,0x26,0x00,0x00,0x00,0x00,0x00,0x00]
+mod32 w6, w2
+
+# CHECK-OBJ-NEW: mod32 w5, -0x7b
+# CHECK-ASM-NEW: encoding: [0x94,0x05,0x00,0x00,0x85,0xff,0xff,0xff]
+mod32 w5, -123