[SOL] Implement atomic swap

LucasSte · Aug 18, 2024 · c04ae67 · c04ae67
1 parent 2e039cf
commit c04ae67
Show file tree

Hide file tree

Showing 2 changed files with 28 additions and 0 deletions.
diff --git a/llvm/lib/Target/SBF/SBFISelLowering.cpp b/llvm/lib/Target/SBF/SBFISelLowering.cpp
@@ -83,6 +83,7 @@ SBFTargetLowering::SBFTargetLowering(const TargetMachine &TM,
       // Implement custom lowering for all atomic operations
       setOperationAction(ISD::ATOMIC_SWAP, VT, Custom);
       setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
+      setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
       setOperationAction(ISD::ATOMIC_LOAD_ADD, VT, Custom);
       setOperationAction(ISD::ATOMIC_LOAD_AND, VT, Custom);
       setOperationAction(ISD::ATOMIC_LOAD_MAX, VT, Custom);
@@ -312,6 +313,7 @@ void SBFTargetLowering::ReplaceNodeResults(SDNode *N,
     report_fatal_error("Unhandled custom legalization");
   case ISD::ATOMIC_SWAP:
   case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
+  case ISD::ATOMIC_CMP_SWAP:
   case ISD::ATOMIC_LOAD_ADD:
   case ISD::ATOMIC_LOAD_AND:
   case ISD::ATOMIC_LOAD_MAX:
@@ -348,6 +350,7 @@ SDValue SBFTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     return LowerSELECT_CC(Op, DAG);
   case ISD::ATOMIC_SWAP:
   case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
+  case ISD::ATOMIC_CMP_SWAP:
   case ISD::ATOMIC_LOAD_ADD:
   case ISD::ATOMIC_LOAD_AND:
   case ISD::ATOMIC_LOAD_MAX:
@@ -918,6 +921,9 @@ SDValue SBFTargetLowering::LowerATOMICRMW(SDValue Op, SelectionDAG &DAG) const {
         DAG.getBoolConstant(false, DL, RetFlagVT, RetFlagVT), ISD::SETEQ);
     break;
   }
+  case ISD::ATOMIC_CMP_SWAP:
+    NewVal = DAG.getSelectCC(DL, Load, Cmp, Val, Load, ISD::SETEQ);
+    break;
   case ISD::ATOMIC_LOAD_ADD:
     NewVal = DAG.getNode(ISD::ADD, DL, ValVT, Load, Val);
     break;

diff --git a/llvm/test/CodeGen/SBF/atomics_sbf.ll b/llvm/test/CodeGen/SBF/atomics_sbf.ll
@@ -329,4 +329,26 @@ define dso_local void @test_store_32(ptr nocapture %p, i32 %val) local_unnamed_a
 entry:
   store atomic i32 %val, ptr %p seq_cst, align 8
   ret void
+}
+
+; CHECK-LABEL: test_weak_cas_32
+; CHECK: ldxw w4, [r1 + 0]
+; CHECK: mov32 r2, w2
+; CHECK: jeq r4, r2,
+; CHECK: stxw [r1 + 0], w3
+define dso_local void @test_weak_cas_32(i32* nocapture %p, i32 %old, i32 %new) local_unnamed_addr {
+entry:
+  cmpxchg weak i32* %p, i32 %old, i32 %new seq_cst seq_cst
+  ret void
+}
+
+; CHECK-LABEL: test_weak_cas_64
+; CHECK: ldxdw r4, [r1 + 0]
+; CHECK: jeq r4, r2,
+; CHECK: mov64 r3, r4
+; CHECK: stxdw [r1 + 0], r3
+define dso_local void @test_weak_cas_64(i64* nocapture %p, i64 %old, i64 %new) local_unnamed_addr {
+entry:
+  cmpxchg weak i64* %p, i64 %old, i64 %new seq_cst seq_cst
+  ret void
 }