Do not change existing instructions

LucasSte · Nov 22, 2024 · d2964b5 · d2964b5
1 parent 844dd0b
commit d2964b5
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Showing 6 changed files with 31 additions and 22 deletions.
diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.cpp b/llvm/lib/Target/SBF/SBFInstrInfo.cpp
@@ -28,16 +28,22 @@ using namespace llvm;
 SBFInstrInfo::SBFInstrInfo()
     : SBFGenInstrInfo(SBF::ADJCALLSTACKDOWN, SBF::ADJCALLSTACKUP) {}
 
+void SBFInstrInfo::setHasExplicitSext(bool HasExplicitSext) {
+  this->HasExpliciSext = HasExplicitSext;
+}
+
 void SBFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                MachineBasicBlock::iterator I,
                                const DebugLoc &DL, MCRegister DestReg,
                                MCRegister SrcReg, bool KillSrc) const {
   if (SBF::GPRRegClass.contains(DestReg, SrcReg))
     BuildMI(MBB, I, DL, get(SBF::MOV_rr), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
-  else if (SBF::GPR32RegClass.contains(DestReg, SrcReg))
-    BuildMI(MBB, I, DL, get(SBF::MOV_rr_32_exp), DestReg)
+  else if (SBF::GPR32RegClass.contains(DestReg, SrcReg)) {
+    unsigned OpCode = HasExpliciSext ? SBF::MOV_rr_32_exp : SBF::MOV_rr_32_no_sext;
+    BuildMI(MBB, I, DL, get(OpCode), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));
+  }
   else
     llvm_unreachable("Impossible reg-to-reg copy");
 }

diff --git a/llvm/lib/Target/SBF/SBFInstrInfo.h b/llvm/lib/Target/SBF/SBFInstrInfo.h
@@ -58,9 +58,11 @@ class SBFInstrInfo : public SBFGenInstrInfo {
                         MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
                         const DebugLoc &DL,
                         int *BytesAdded = nullptr) const override;
+  void setHasExplicitSext(bool HasExplicitSext);
+
 private:
   void expandMEMCPY(MachineBasicBlock::iterator) const;
-
+  bool HasExpliciSext;
 };
 }
 

diff --git a/llvm/lib/Target/SBF/SBFSubtarget.cpp b/llvm/lib/Target/SBF/SBFSubtarget.cpp
@@ -30,6 +30,7 @@ SBFSubtarget &SBFSubtarget::initializeSubtargetDependencies(const Triple &TT,
                                                             StringRef FS) {
   initializeEnvironment(TT);
   initSubtargetFeatures(CPU, FS);
+  InstrInfo.setHasExplicitSext(ExplicitSignExt);
   return *this;
 }
 

diff --git a/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll b/llvm/test/CodeGen/SBF/32-bit-subreg-alu.ll
@@ -130,7 +130,7 @@
 define dso_local i32 @mov(i32 returned %a) local_unnamed_addr #0 {
 entry:
   ret i32 %a
-; CHECK: mov64 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: mov32 w{{[0-9]+}}, w{{[0-9]+}}
 }
 
 ; Function Attrs: norecurse nounwind readnone
@@ -320,6 +320,6 @@ entry:
 define dso_local i32 @neg(i32 %a) local_unnamed_addr #0 {
 entry:
   %sub = sub nsw i32 0, %a
-; CHECK: mov64 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK: mov32 w{{[0-9]+}}, w{{[0-9]+}}
   ret i32 %sub
 }
diff --git a/llvm/test/CodeGen/SBF/atomics_sbf.ll b/llvm/test/CodeGen/SBF/atomics_sbf.ll
@@ -2,7 +2,7 @@
 ;
 ; CHECK-LABEL: test_load_add_32
 ; CHECK: ldxw w0, [r1 + 0]
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: add32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local i32 @test_load_add_32(i32* nocapture %p, i32 %v) local_unnamed_addr {
@@ -25,7 +25,7 @@ entry:
 
 ; CHECK-LABEL: test_load_sub_32
 ; CHECK: ldxw w0, [r1 + 0]
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: sub32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local i32 @test_load_sub_32(i32* nocapture %p, i32 %v) local_unnamed_addr {
@@ -68,7 +68,7 @@ entry:
 ; CHECK-LABEL: test_cas_32
 ; CHECK: ldxw w0, [r1 + 0]
 ; CHECK: jeq r0, r2,
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: stxw [r1 + 0], w3
 define dso_local i32 @test_cas_32(i32* nocapture %p, i32 %old, i32 %new) local_unnamed_addr {
 entry:
@@ -91,7 +91,7 @@ entry:
 
 ; CHECK-LABEL: test_load_and_32
 ; CHECK: ldxw w0, [r1 + 0]
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: and32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local i32 @test_load_and_32(i32* nocapture %p, i32 %v) local_unnamed_addr {
@@ -113,7 +113,7 @@ entry:
 
 ; CHECK-LABEL: test_load_nand_32
 ; CHECK: ldxw w0, [r1 + 0]
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: and32 w3, w2
 ; CHECK: xor32 w3, -1
 ; CHECK: stxw [r1 + 0], w3
@@ -137,7 +137,7 @@ entry:
 
 ; CHECK-LABEL: test_load_or_32
 ; CHECK: ldxw w0, [r1 + 0]
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: or32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local i32 @test_load_or_32(i32* nocapture %p, i32 %v) local_unnamed_addr {
@@ -159,7 +159,7 @@ entry:
 
 ; CHECK-LABEL: test_load_xor_32
 ; CHECK: ldxw w0, [r1 + 0]
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: xor32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local i32 @test_load_xor_32(i32* nocapture %p, i32 %v) local_unnamed_addr {
@@ -187,9 +187,9 @@ entry:
 ; CHECK: mov32 r5, w2
 ; CHECK: lsh64 r5, 32
 ; CHECK: arsh64 r5, 32
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: jslt r4, r5, LBB16_2
-; CHECK: mov64 w3, w2
+; CHECK: mov32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local i32 @test_min_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
 entry:
@@ -217,9 +217,9 @@ entry:
 ; CHECK: mov32 r5, w2
 ; CHECK: lsh64 r5, 32
 ; CHECK: arsh64 r5, 32
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: jsgt r4, r5, LBB18_2
-; CHECK: mov64 w3, w2
+; CHECK: mov32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local  i32 @test_max_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
 entry:
@@ -242,9 +242,9 @@ entry:
 ; CHECK-LABEL: test_umin_32
 ; CHECK: ldxw w0, [r1 + 0]
 ; CHECK: mov32 r4, w2
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: jlt r0, r4,
-; CHECK: mov64 w3, w2
+; CHECK: mov32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local  i32 @test_umin_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
 entry:
@@ -267,9 +267,9 @@ entry:
 ; CHECK-LABEL: test_umax_32
 ; CHECK: ldxw w0, [r1 + 0]
 ; CHECK: mov32 r4, w2
-; CHECK: mov64 w3, w0
+; CHECK: mov32 w3, w0
 ; CHECK: jgt r0, r4,
-; CHECK: mov64 w3, w2
+; CHECK: mov32 w3, w2
 ; CHECK: stxw [r1 + 0], w3
 define dso_local  i32 @test_umax_32(i32* nocapture %ptr, i32 %v) local_unnamed_addr #0 {
 entry:
@@ -306,7 +306,7 @@ entry:
 ; CHECK: ldxw w0, [r1 + 0]
 ; CHECK: mov32 w2, 0
 ; CHECK: jeq r0, 0, LBB25_2
-; CHECK: mov64 w2, w0
+; CHECK: mov32 w2, w0
 ; CHECK: LBB25_2:
 ; CHECK: stxw [r1 + 0], w2
 define dso_local i32 @test_load_32(ptr nocapture %p) local_unnamed_addr {

diff --git a/llvm/test/CodeGen/SBF/pqr-class.ll b/llvm/test/CodeGen/SBF/pqr-class.ll
@@ -80,7 +80,7 @@ entry:
 ; CHECK-v1: mod32 w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK-v1: div32 w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}}
-; CHECK-v1: mov64 w{{[0-9]+}}, w{{[0-9]+}}
+; CHECK-v1: mov32 w{{[0-9]+}}, w{{[0-9]+}}
 ; CHECK-v1: mod32 w{{[0-9]+}}, 17
 ; CHECK-v1: div32 w{{[0-9]+}}, 7
 ; CHECK-v1: add32 w{{[0-9]+}}, w{{[0-9]+}}