Labels · NYU-Processor-Design/nyu-core

bug

Something isn't working

Module that was canceled or removed from design

Items that have been connected in higher level modules but have not been tested with the entire core

This issue or pull request already exists

New feature or request

Task is being worked on

Modules that are part of a higher level connection module and need to be interfaced or connected

Module that needs to be implemented

Module that needs to be outlined

on hold

Items whose development is on hold

question

Further information is requested

todo

Task needs to be started

Improvement needs to be made to verilog code

wontfix

This will not be worked on

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