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arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #27

arch-riscv: default disable vs bit, set misa with B-ext, update ref-so

arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #27

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XS-GEM5 - Test new simulation script on RV64GCB

succeeded Aug 20, 2024 in 17m 18s