cpu-o3: IQ with regfile read port arbitration and

move scheduler to one config python file

configs/common/FUScheduler.py

@@ -0,0 +1,182 @@
+
+
+from m5.SimObject import SimObject
+from m5.params import *
+from m5.objects.FuncUnit import *
+from m5.objects.FuncUnitConfig import *
+from m5.objects.FUPool import *
+
+#  must be consistent with issue_queue.cc
+maxTotalRFPorts = (1 << 6) - 1
+# portid, priority
+def IntRD(id, p):
+    # [7:6] [5:2] [1:0]
+    assert id < 16
+    assert p < 4
+    ret = (0 << 6) | (id << 2) | (p)
+    return ret
+
+def FpRD(id, p):
+    # [7:6] [5:2] [1:0]
+    assert id < 16
+    assert p < 4
+    ret = (1 << 6) | (id << 2) | (p)
+    return ret
+
+class ECoreScheduler(Scheduler):
+    IQs = [
+        IssueQue(name='intIQ0' , inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU(), IntBRU()]),
+            IssuePort(fu=[IntALU(), IntBRU()])
+        ]),
+        IssueQue(name='intIQ1' , inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU(), IntBRU()]),
+            IssuePort(fu=[IntALU(), IntBRU()])
+        ]),
+        IssueQue(name='intIQ2' , inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntMult(), IntDiv(), IntMisc()])
+        ]),
+        IssueQue(name='memIQ0' , inports=2, size=2*16, oports=[
+            IssuePort(fu=[ReadPort()])
+        ]),
+        IssueQue(name='memIQ1' , inports=2, size=2*16, oports=[
+            IssuePort(fu=[RdWrPort()])
+        ]),
+        IssueQue(name='fpIQ0' , inports=2, size=18, oports=[
+            IssuePort(fu=[FP_ALU(), FP_MAC()]),
+            IssuePort(fu=[FP_ALU(), FP_MAC()])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='fpIQ1' , inports=2, size=18, oports=[
+            IssuePort(fu=[FP_MISC(), FP_SLOW()])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='vecIQ0' , inports=2, size=16, oports=[
+            IssuePort(fu=[SIMD_Unit()]),
+            IssuePort(fu=[SIMD_Unit()])
+        ], scheduleToExecDelay=3),
+    ]
+    xbarWakeup = True
+
+class ECore2ReadScheduler(Scheduler):
+    IQs = [
+        IssueQue(name='intIQ0' , inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU(), IntBRU()]),
+            IssuePort(fu=[IntALU(), IntBRU()])
+        ]),
+        IssueQue(name='intIQ1' , inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU(), IntBRU()]),
+            IssuePort(fu=[IntALU(), IntBRU()])
+        ]),
+        IssueQue(name='intIQ2' , inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntMult(), IntDiv(), IntMisc()])
+        ]),
+        IssueQue(name='memIQ0' , inports=2, size=2*16, oports=[
+            IssuePort(fu=[ReadPort()]),
+            IssuePort(fu=[ReadPort()])
+        ]),
+        IssueQue(name='memIQ1' , inports=2, size=2*16, oports=[
+            IssuePort(fu=[WritePort()])
+        ]),
+        IssueQue(name='fpIQ0' , inports=2, size=18, oports=[
+            IssuePort(fu=[FP_ALU(), FP_MAC()]),
+            IssuePort(fu=[FP_ALU(), FP_MAC()])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='fpIQ1' , inports=2, size=18, oports=[
+            IssuePort(fu=[FP_MISC()])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='fpIQ4' , inports=2, size=18, oports=[
+            IssuePort(fu=[FP_SLOW()])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='vecIQ0' , inports=2, size=16, oports=[
+            IssuePort(fu=[SIMD_Unit()]),
+            IssuePort(fu=[SIMD_Unit()])
+        ], scheduleToExecDelay=3),
+    ]
+    xbarWakeup = True
+
+
+class KunminghuScheduler(Scheduler):
+    IQs = [
+        IssueQue(name='intIQ0', inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU(), IntMult()], rp=[IntRD(0, 0), IntRD(1, 0)]),
+            IssuePort(fu=[IntBRU()], rp=[IntRD(6, 1), IntRD(7, 1)])
+        ]),
+        IssueQue(name='intIQ1', inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU(), IntMult()], rp=[IntRD(2, 0), IntRD(3, 0)]),
+            IssuePort(fu=[IntBRU()], rp=[IntRD(4, 1), IntRD(5, 1)])
+        ]),
+        IssueQue(name='intIQ2', inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU()], rp=[IntRD(4, 0), IntRD(5, 0)]),
+            IssuePort(fu=[IntBRU(), IntMisc()], rp=[IntRD(2, 1), IntRD(3, 1)])
+        ]),
+        IssueQue(name='intIQ3', inports=2, size=2*12, oports=[
+            IssuePort(fu=[IntALU()], rp=[IntRD(6, 0), IntRD(7, 0)]),
+            IssuePort(fu=[IntDiv()], rp=[IntRD(0, 1), IntRD(1, 1)])
+        ]),
+        IssueQue(name='load0', inports=1, size=16, oports=[
+            IssuePort(fu=[ReadPort()], rp=[IntRD(8, 0)])
+        ]),
+        IssueQue(name='load1', inports=1, size=16, oports=[
+            IssuePort(fu=[ReadPort()], rp=[IntRD(9, 0)])
+        ]),
+        IssueQue(name='load2', inports=1, size=16, oports=[
+            IssuePort(fu=[ReadPort()], rp=[IntRD(10, 0)])
+        ]),
+        IssueQue(name='store0', inports=1, size=16, oports=[
+            IssuePort(fu=[WritePort()], rp=[IntRD(7, 2), IntRD(5,2), FpRD(12,0)])
+        ]),
+        IssueQue(name='store1', inports=1, size=16, oports=[
+            IssuePort(fu=[WritePort()], rp=[IntRD(6, 2), IntRD(3,2), FpRD(13,0)])
+        ]),
+        IssueQue(name='fpIQ0', inports=2, size=18, oports=[
+            IssuePort(fu=[FP_ALU(), FP_MISC(), FP_MAC()], rp=[FpRD(0,0), FpRD(1, 0), FpRD(2,0)])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='fpIQ1', inports=2, size=18, oports=[
+            IssuePort(fu=[FP_ALU(), FP_MAC()], rp=[FpRD(3,0), FpRD(4,0), FpRD(5,0)])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='fpIQ2', inports=2, size=18, oports=[
+            IssuePort(fu=[FP_ALU(), FP_MAC()], rp=[FpRD(6,0), FpRD(7,0), FpRD(8,0)])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='fpIQ3', inports=2, size=18, oports=[
+            IssuePort(fu=[FP_ALU(), FP_MAC()], rp=[FpRD(9,0), FpRD(10,0), FpRD(11,0)])
+        ], scheduleToExecDelay=3),
+        IssueQue(name='fpIQ4', inports=2, size=18, oports=[
+            IssuePort(fu=[FP_SLOW()], rp=[FpRD(2,1), FpRD(5,1)]),
+            IssuePort(fu=[FP_SLOW()], rp=[FpRD(8,1), FpRD(11,1)]),
+        ], scheduleToExecDelay=3),
+        IssueQue(name='vecIQ0', inports=5, size=16+16+10, oports=[
+            IssuePort(fu=[SIMD_Unit()]),
+            IssuePort(fu=[SIMD_Unit()]),
+            IssuePort(fu=[SIMD_Unit()]),
+            IssuePort(fu=[SIMD_Unit()]),
+            IssuePort(fu=[SIMD_Unit()])
+        ], scheduleToExecDelay=3),
+    ]
+    __int_bank = ['intIQ0', 'intIQ1', 'intIQ2', 'intIQ3', 'load0', 'load1', 'load2', 'store0', 'store1']
+    __fp_bank = ['fpIQ0', 'fpIQ1', 'fpIQ2', 'fpIQ3', 'fpIQ4', 'store0', 'store1']
+    specWakeupNetwork = [
+        SpecWakeupChannel(srcIQ='intIQ0', dstIQ=__int_bank),
+        SpecWakeupChannel(srcIQ='intIQ1', dstIQ=__int_bank),
+        SpecWakeupChannel(srcIQ='intIQ2', dstIQ=__int_bank),
+        SpecWakeupChannel(srcIQ='intIQ3', dstIQ=__int_bank),
+        SpecWakeupChannel(srcIQ='fpIQ0', dstIQ=__fp_bank),
+        SpecWakeupChannel(srcIQ='fpIQ1', dstIQ=__fp_bank),
+        SpecWakeupChannel(srcIQ='fpIQ2', dstIQ=__fp_bank),
+        SpecWakeupChannel(srcIQ='fpIQ3', dstIQ=__fp_bank),
+        # SpecWakeupChannel(srcIQ='fpIQ4', dstIQ=__fp_bank),
+        SpecWakeupChannel(srcIQ='load0', dstIQ=__int_bank),
+        SpecWakeupChannel(srcIQ='load1', dstIQ=__int_bank),
+        SpecWakeupChannel(srcIQ='load2', dstIQ=__int_bank),
+    ]
+
+
+    def __init__(self, *args, **kwargs):
+        super().__init__(*args, **kwargs)
+        # self.disableAllRegArb()
+
+    def disableAllRegArb(self):
+        print("Disable regfile arbitration")
+        for iq in self.IQs:
+            for port in iq.oports:
+                port.rp.clear()
+
+DefaultScheduler = KunminghuScheduler

configs/example/fs.py

@@ -62,6 +62,7 @@
 from common import ObjectList
 from common.Caches import *
 from common import Options
+from common.FUScheduler import *
 
 def cmd_line_template():
     if args.command_line and args.command_line_file:
@@ -150,6 +151,7 @@ def build_test_system(np):
                     for i in range(np)]
     if args.xiangshan_system:
         for cpu in test_sys.cpu:
+            cpu.scheduler = DefaultScheduler()
             cpu.mmu.pma_checker = PMAChecker(
                 uncacheable=[AddrRange(0, size=0x80000000)])
     if args.enable_arch_db:

configs/example/xiangshan.py

@@ -22,6 +22,42 @@
 from common import XSConfig
 from common.Caches import *
 from common import Options
+from common.FUScheduler import *
+
+class XiangshanCore(RiscvO3CPU):
+    scheduler = KunminghuScheduler()
+
+class XiangshanECore(XiangshanCore):
+    fetchWidth = 8
+    decodeWidth = 4
+    renameWidth = 4
+
+    numROBEntries = 150
+    LQEntries = 48
+    SQEntries = 32
+    numPhysIntRegs = 108
+    numPhysFloatRegs = 112
+    numPhysVecRegs = 112
+    numPhysVecPredRegs = 36
+    numPhysCCRegs = 0
+    numPhysRMiscRegs = 40
+    scheduler = ECoreScheduler()
+
+class XiangshanECore2Read(XiangshanCore):
+    fetchWidth = 8
+    decodeWidth = 4
+    renameWidth = 4
+
+    numROBEntries = 150
+    LQEntries = 48
+    SQEntries = 32
+    numPhysIntRegs = 108
+    numPhysFloatRegs = 112
+    numPhysVecRegs = 112
+    numPhysVecPredRegs = 36
+    numPhysCCRegs = 0
+    numPhysRMiscRegs = 40
+    scheduler = ECore2ReadScheduler()
 
 def build_test_system(np, args):
     assert buildEnv['TARGET_ISA'] == "riscv"

src/arch/riscv/RiscvCPU.py

@@ -54,38 +54,3 @@ class RiscvO3CPU(BaseO3CPU, RiscvCPU):
 
 class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
     mmu = RiscvMMU()
-
-class XiangshanCore(RiscvO3CPU):
-    scheduler = KunminghuScheduler()
-
-class XiangshanECore(XiangshanCore):
-    fetchWidth = 8
-    decodeWidth = 4
-    renameWidth = 4
-
-    numROBEntries = 150
-    LQEntries = 48
-    SQEntries = 32
-    numPhysIntRegs = 108
-    numPhysFloatRegs = 112
-    numPhysVecRegs = 112
-    numPhysVecPredRegs = 36
-    numPhysCCRegs = 0
-    numPhysRMiscRegs = 40
-    scheduler = ECoreScheduler()
-
-class XiangshanECore2Read(XiangshanCore):
-    fetchWidth = 8
-    decodeWidth = 4
-    renameWidth = 4
-
-    numROBEntries = 150
-    LQEntries = 48
-    SQEntries = 32
-    numPhysIntRegs = 108
-    numPhysFloatRegs = 112
-    numPhysVecRegs = 112
-    numPhysVecPredRegs = 36
-    numPhysCCRegs = 0
-    numPhysRMiscRegs = 40
-    scheduler = ECore2ReadScheduler()

src/cpu/o3/BaseO3CPU.py

@@ -132,7 +132,9 @@ def support_take_over(cls):
                "Issue/Execute/Writeback delay")
     executeToWriteBackDelay = Param.Cycles(1, "Execute to issue delay")
 
-    dispWidth = Param.Unsigned(6, "Each DispQue dispatch width")
+    numDQEntries = VectorParam.Unsigned([32, 16, 16], "Number of entries in the dispQue, (Int, Float/Vector, Mem)")
+    dispWidth = VectorParam.Unsigned([8, 6, 6], "Each DispQue dispatch width")
+
     wbWidth = Param.Unsigned(20, "Writeback width")
 
     iewToCommitDelay = Param.Cycles(1, "Issue/Execute/Writeback to commit "
@@ -157,7 +159,7 @@ def support_take_over(cls):
     SQEntries = Param.Unsigned(64, "Number of store queue entries")
 
     SbufferEntries = Param.Unsigned(16, "Number of store buffer entries")
-    SbufferEvictThreshold = Param.Unsigned(8, "store buffer eviction threshold")
+    SbufferEvictThreshold = Param.Unsigned(7, "store buffer eviction threshold")
     storeBufferInactiveThreshold = Param.Unsigned(800, "store buffer writeback timeout threshold")
 
     LSQDepCheckShift = Param.Unsigned(0,
@@ -190,7 +192,6 @@ def support_take_over(cls):
     numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers")
     numPhysRMiscRegs = Param.Unsigned(40, "Number of physical renameable misc registers")
 
-    numDQEntries = Param.Unsigned(18, "Number of entries in the dispQue")
     numROBEntries = Param.Unsigned(320, "Number of reorder buffer entries")
 
     smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
@@ -210,7 +211,7 @@ def support_take_over(cls):
                                        "Branch Predictor")
     needsTSO = Param.Bool(False, "Enable TSO Memory model")
 
-    scheduler = Param.Scheduler(KunminghuScheduler(), "")
+    scheduler = Param.Scheduler("")
 
     arch_db = Param.ArchDBer(Parent.any, "Arch DB")