arch-riscv: default disable vs bit, set misa with B-ext, update ref-so

OpenXiangShan · Aug 20, 2024 · c4db87f · c4db87f
1 parent ed6980e
commit c4db87f
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Showing 5 changed files with 29 additions and 28 deletions.
diff --git a/.github/workflows/autotest/gem5.cfg b/.github/workflows/autotest/gem5.cfg
@@ -14,8 +14,8 @@ log_root = ./log_root
 #编译线程
 compile_thread = 70
 #gcpt路径
-gcpt_path = /nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcb-restorer.bin
-ref_so_path = /nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-ref.so
+gcpt_path = /nfs/home/share/gem5_shared_tools/normal-gcb-restorer.bin
+ref_so_path = /nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so
 
 set_var = export NEMU_HOME={ref_so_path}
 

diff --git a/.github/workflows/gem5.yml b/.github/workflows/gem5.yml
@@ -74,8 +74,8 @@ jobs:
         run: CC=gcc CXX=g++ scons build/RISCV/gem5.opt --linker=gold -j64
       - name: XS-GEM5 - Test xiangshan.py simulation scripts
         run: |
-          export GCBV_REF_SO="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-ref.so"
-          export GCB_RESTORER="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcb-restorer.bin"
+          export GCBV_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so"
+          export GCB_RESTORER="/nfs/home/share/gem5_shared_tools/normal-gcb-restorer.bin"
           export GEM5_HOME=$(pwd)
           mkdir -p $GEM5_HOME/util/xs_scripts/test
           cd $GEM5_HOME/util/xs_scripts/test
@@ -101,8 +101,8 @@ jobs:
         run: CC=gcc CXX=g++ scons build/RISCV/gem5.opt --linker=gold -j64
       - name: XS-GEM5 - Test xiangshan.py simulation scripts
         run: |
-          export GCBV_REF_SO="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-ref.so"
-          export GCBV_RESTORER="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcbv-restorer.bin"
+          export GCBV_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-nemu-4332a525-so"
+          export GCBV_RESTORER="/nfs/home/share/gem5_shared_tools/gcbv-restorer.bin"
           export GEM5_HOME=$(pwd)
           mkdir -p $GEM5_HOME/util/xs_scripts/test_v
           cd $GEM5_HOME/util/xs_scripts/test_v
@@ -120,8 +120,8 @@ jobs:
           CC=clang CXX=clang++ scons build/RISCV_CHI/gem5.opt -j 48 --gold-linker
       - name: XS-GEM5 - Test xiangshan.py simulation scripts
         run: |
-          export GCBV_MULTI_CORE_REF_SO="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/nemu-gcbv-multi-core-ref.so"
-          export GCB_MULTI_CORE_RESTORER="/nfs-nvme/home/share/zyy/shared_payloads/gem5-release/2024-05-14/gcb-2core-restorer.bin"
+          export GCBV_MULTI_CORE_REF_SO="/nfs/home/share/gem5_shared_tools/riscv64-dualcore-nemu-4332a525-so"
+          export GCB_MULTI_CORE_RESTORER="/nfs/home/share/gem5_shared_tools/gcb-2core-restorer.bin"
           export GEM5_HOME=$(pwd)
           mkdir -p $GEM5_HOME/util/xs_scripts/test_multi_core
           cd $GEM5_HOME/util/xs_scripts/test_multi_core

diff --git a/README.md b/README.md
@@ -220,10 +220,10 @@ If above branches are not working, you can try the following commits:
 
 | Checkpoint Type | reference design | GCPT restorer 
 | ---------- | --------- | --------- |
-| RV64GCB | NEMU 732e4ccd + riscv64-gem5-ref_defconfig | NEMU 732e4ccd |
-| RV64GCBV      | NEMU 732e4ccd + riscv64-gem5-ref_defconfig | NEMU b966d274 |
-| RV64GCB multi-core | NEMU 732e4ccd + riscv64-gem5-multicore-ref_defconfig | Download Binary from release; Code release soon |
-| RV64GCBV multi-core | NEMU 732e4ccd + riscv64-gem5-multicore-ref_defconfig | ~~NOT available yet~~ |
+| RV64GCB | NEMU 4332a525 + riscv64-gem5-ref_defconfig | NEMU 732e4ccd |
+| RV64GCBV      | NEMU 4332a525 + riscv64-gem5-ref_defconfig | NEMU b966d274 |
+| RV64GCB multi-core | NEMU 4332a525 + riscv64-gem5-multicore-ref_defconfig | Download Binary from release; Code release soon |
+| RV64GCBV multi-core | NEMU 4332a525 + riscv64-gem5-multicore-ref_defconfig | ~~NOT available yet~~ |
 
 
 **NOTE**:

diff --git a/configs/example/fs.py b/configs/example/fs.py
@@ -484,6 +484,7 @@ def build_drive_system(np):
 if args.enable_riscv_vector:
     print("Enable riscv vector difftest, need riscv vector-supported gcpt restore and diff-ref-so")
     test_sys.enable_riscv_vector = True
+    test_sys.gcpt_restorer_size_limit = 0x1000
     for cpu in test_sys.cpu:
         cpu.enable_riscv_vector = True
 

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
@@ -257,13 +257,13 @@ void ISA::clear()
     std::fill(miscRegFile.begin(), miscRegFile.end(), 0);
 
     miscRegFile[MISCREG_PRV] = PRV_M;
-    miscRegFile[MISCREG_ISA] = (2ULL << MXL_OFFSET) | 0x34112D;
+    miscRegFile[MISCREG_ISA] = 0x800000000034112f;
     miscRegFile[MISCREG_VENDORID] = 0;
     miscRegFile[MISCREG_ARCHID] = 0;
     miscRegFile[MISCREG_IMPID] = 0;
     if (FullSystem) {
         // Xiangshan assume machine boots with FS off
-        miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) | (1ULL <<VS_OFFSET);
+        miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET);
     } else {
         // SE assumes process starts with FS on
         miscRegFile[MISCREG_STATUS] = (2ULL << UXL_OFFSET) | (2ULL << SXL_OFFSET) |
@@ -517,20 +517,20 @@ ISA::setMiscReg(int misc_reg, RegVal val)
             break;
           case MISCREG_ISA:
             {
-                auto cur_val = readMiscRegNoEffect(misc_reg);
-                // only allow to disable compressed instructions
-                // if the following instruction is 4-byte aligned
-                if ((val & ISA_EXT_C_MASK) == 0 &&
-                        bits(tc->pcState().as<RiscvISA::PCState>().npc(),
-                            2, 0) != 0) {
-                    val |= cur_val & ISA_EXT_C_MASK;
-                }
-
-                if ((val & ISA_EXT_H_MASK) != 0) {
-                    // Do not allow to enable RVH because not implemented yet
-                    val &= ~ISA_EXT_H_MASK;
-                }
-                setMiscRegNoEffect(misc_reg, val);
+                // auto cur_val = readMiscRegNoEffect(misc_reg);
+                // // only allow to disable compressed instructions
+                // // if the following instruction is 4-byte aligned
+                // if ((val & ISA_EXT_C_MASK) == 0 &&
+                //         bits(tc->pcState().as<RiscvISA::PCState>().npc(),
+                //             2, 0) != 0) {
+                //     val |= cur_val & ISA_EXT_C_MASK;
+                // }
+
+                // if ((val & ISA_EXT_H_MASK) != 0) {
+                //     // Do not allow to enable RVH because not implemented yet
+                //     val &= ~ISA_EXT_H_MASK;
+                // }
+                // setMiscRegNoEffect(misc_reg, val);
             }
             break;
           case MISCREG_STATUS: