[SC64][FW] Verilator tests + many bugfixes in the FPGA code (#75)

Polprzewodnikowy · Jul 21, 2024 · 1b71b4a · 1b71b4a
1 parent 5e33e51
commit 1b71b4a
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Showing 24 changed files with 1,166 additions and 320 deletions.
diff --git a/fw/project/lcmxo2/sc64.ldf b/fw/project/lcmxo2/sc64.ldf
@@ -3,6 +3,9 @@
     <Options/>
     <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="release">
         <Options VerilogStandard="System Verilog" def_top="top" top="top"/>
+        <Source name="../../rtl/memory/dma_scb.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
         <Source name="../../rtl/memory/mem_bus.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
@@ -12,6 +15,9 @@
         <Source name="../../rtl/sd/sd_scb.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>
+        <Source name="../../rtl/usb/usb_scb.sv" type="Verilog" type_short="Verilog">
+            <Options VerilogStandard="System Verilog"/>
+        </Source>
         <Source name="../../rtl/fifo/fifo_bus.sv" type="Verilog" type_short="Verilog">
             <Options VerilogStandard="System Verilog"/>
         </Source>

diff --git a/fw/project/lcmxo2/sc64.lpf b/fw/project/lcmxo2/sc64.lpf
@@ -214,7 +214,7 @@ LOCATE COMP "usb_miso" SITE "10" ;
 LOCATE COMP "usb_pwrsav" SITE "2" ;
 SYSCONFIG SDM_PORT=DISABLE I2C_PORT=ENABLE ;
 VOLTAGE 3.300 V;
-FREQUENCY NET "clk" 100.000000 MHz PAR_ADJ 10.000000 ;
+FREQUENCY NET "clk" 100.000000 MHz ;
 BLOCK PATH TO PORT "mcu_int" ;
 BLOCK PATH TO PORT "n64_irq" ;
 BLOCK PATH FROM PORT "usb_pwrsav" ;

diff --git a/fw/rtl/fifo/fifo_bus.sv b/fw/rtl/fifo/fifo_bus.sv
@@ -1,35 +1,29 @@
 interface fifo_bus ();
 
     logic rx_empty;
-    logic rx_almost_empty;
     logic rx_read;
     logic [7:0] rx_rdata;
 
     logic tx_full;
-    logic tx_almost_full;
     logic tx_write;
     logic [7:0] tx_wdata;
 
     modport controller (
         input rx_empty,
-        input rx_almost_empty,
         output rx_read,
         input rx_rdata,
 
         input tx_full,
-        input tx_almost_full,
         output tx_write,
         output tx_wdata
     );
 
     modport fifo (
         output rx_empty,
-        output rx_almost_empty,
         input rx_read,
         output rx_rdata,
 
         output tx_full,
-        output tx_almost_full,
         input tx_write,
         input tx_wdata
     );

diff --git a/fw/rtl/fifo/fifo_junction.sv b/fw/rtl/fifo/fifo_junction.sv
@@ -11,16 +11,12 @@ module fifo_junction (
         dev_bus.tx_wdata = cfg_bus.tx_write ? cfg_bus.tx_wdata : dma_bus.tx_wdata;
 
         cfg_bus.rx_empty = dev_bus.rx_empty;
-        cfg_bus.rx_almost_empty = dev_bus.rx_almost_empty;
         cfg_bus.rx_rdata = dev_bus.rx_rdata;
         cfg_bus.tx_full = dev_bus.tx_full;
-        cfg_bus.tx_almost_full = dev_bus.tx_almost_full;
 
         dma_bus.rx_empty = dev_bus.rx_empty;
-        dma_bus.rx_almost_empty = dev_bus.rx_almost_empty;
         dma_bus.rx_rdata = dev_bus.rx_rdata;
         dma_bus.tx_full = dev_bus.tx_full;
-        dma_bus.tx_almost_full = dev_bus.tx_almost_full;
     end
 
 endmodule
diff --git a/fw/rtl/memory/dma_scb.sv b/fw/rtl/memory/dma_scb.sv
@@ -0,0 +1,31 @@
+interface dma_scb ();
+
+    logic start;
+    logic stop;
+    logic busy;
+    logic direction;
+    logic byte_swap;
+    logic [26:0] starting_address;
+    logic [26:0] transfer_length;
+
+    modport controller (
+        output start,
+        output stop,
+        input busy,
+        output direction,
+        output byte_swap,
+        output starting_address,
+        output transfer_length
+    );
+
+    modport dma (
+        input start,
+        input stop,
+        output busy,
+        input direction,
+        input byte_swap,
+        input starting_address,
+        input transfer_length
+    );
+
+endinterface