[SC64][FW][SW] Made CPU boot process simpler, UART is now an optional…

… module (#12)

.github/workflows/main.yml

@@ -22,7 +22,7 @@ jobs:
           submodules: true
 
       - name: Build script
-        run: ./docker_build.sh release
+        run: ./docker_build.sh release --force-clean
 
       - name: Upload artifact
         uses: actions/upload-artifact@v2

.gitmodules

@@ -1,4 +1,4 @@
-[submodule "fw/cpu/picorv32"]
+[submodule "fw/picorv32"]
 	path = fw/picorv32
 	url = https://github.com/cliffordwolf/picorv32.git
 	ignore = dirty

build.sh

@@ -19,6 +19,9 @@ BUILT_FPGA=false
 BUILT_UPDATE=false
 BUILT_RELEASE=false
 
+FORCE_CLEAN=false
+SKIP_FPGA_REBUILD=false
+
 build_cic () {
     if [ "$BUILT_CIC" = true ]; then return; fi
 
@@ -33,7 +36,10 @@ build_n64 () {
     if [ "$BUILT_N64" = true ]; then return; fi
 
     pushd sw/n64
-    make clean all
+    if [ "$FORCE_CLEAN" = true ]; then
+        make clean
+    fi
+    make all
     popd
 
     BUILT_N64=true
@@ -43,7 +49,10 @@ build_riscv () {
     if [ "$BUILT_RISCV" = true ]; then return; fi
 
     pushd sw/riscv
-    make clean all
+    if [ "$FORCE_CLEAN" = true ]; then
+        make clean
+    fi
+    make all
     popd
 
     BUILT_RISCV=true
@@ -56,7 +65,11 @@ build_fpga () {
     build_riscv
 
     pushd fw
-    quartus_sh --flow compile ./SummerCart64.qpf
+    if [ "$SKIP_FPGA_REBUILD" = true ] && [ -f output_files/SummerCart64.sof ]; then
+        quartus_cpf -c SummerCart64.cof
+    else
+        quartus_sh --flow compile ./SummerCart64.qpf
+    fi
     popd
 
     BUILT_FPGA=true
@@ -82,25 +95,29 @@ build_release () {
     build_cic
     build_update
 
-    if [[ -e "./${PACKAGE_FILE_NAME}.zip" ]]; then
+    if [ -e "./${PACKAGE_FILE_NAME}.zip" ]; then
         rm -f "./${PACKAGE_FILE_NAME}.zip"
     fi
-    zip -r "./${PACKAGE_FILE_NAME}.zip" ${FILES[@]}
+    zip -j -r "./${PACKAGE_FILE_NAME}.zip" ${FILES[@]}
 
     BUILT_RELEASE=true
 }
 
 print_usage () {
     echo "builder script for SummerCart64"
-    echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [--help]"
+    echo "usage: ./build.sh [cic] [n64] [riscv] [fpga] [update] [release] [-c] [-s] [--help]"
     echo "parameters:"
-    echo "  cic - assemble UltraCIC-III software"
-    echo "  n64 - compile N64 bootloader software"
-    echo "  riscv - compile cart governor software"
-    echo "  fpga - compile FPGA design (triggers 'n64' and 'riscv' build)"
-    echo "  update - convert programming .pof file to raw binary for user upgrade (triggers 'fpga' build)"
-    echo "  release - collect and zip files for release (triggers 'cic' and 'update' build)"
-    echo "  --help - print this guide"
+    echo "  cic       - assemble UltraCIC-III software"
+    echo "  n64       - compile N64 bootloader software"
+    echo "  riscv     - compile cart governor software"
+    echo "  fpga      - compile FPGA design (triggers 'n64' and 'riscv' build)"
+    echo "  update    - convert programming .pof file to raw binary for self-upgrade (triggers 'fpga' build)"
+    echo "  release   - collect and zip files for release (triggers 'cic' and 'update' build)"
+    echo "  -c | --force-clean"
+    echo "            - clean software compilation result directories before build"
+    echo "  -s | --skip-fpga-rebuild"
+    echo "            - do not recompile whole FPGA design if it's already done, just update software binaries"
+    echo "  --help    - print this guide"
 }
 
 if test $# -eq 0; then
@@ -137,6 +154,12 @@ while test $# -gt 0; do
         release)
             TRIGGER_RELEASE=true
             ;;
+        -c|--force-clean)
+            FORCE_CLEAN=true
+            ;;
+        -s|--skip-fpga-rebuild)
+            SKIP_FPGA_REBUILD=true
+            ;;
         --help)
             print_usage
             exit 0

fw/SummerCart64.cof

@@ -28,7 +28,7 @@
 		<epof>0</epof>
 		<ufm_source>2</ufm_source>
 		<ufm_filepath>../sw/n64/build/SummerLoader64.hex</ufm_filepath>
-		<cfm0_filepath>../sw/riscv/build/controller.hex</cfm0_filepath>
+		<cfm0_filepath>../sw/riscv/build/governor.hex</cfm0_filepath>
 		<cfm0_file_start_addr>305152</cfm0_file_start_addr>
 	</MAX10_device_options>
 	<advanced_options>

fw/SummerCart64.qsf

@@ -19,7 +19,7 @@
 #
 # Quartus Prime
 # Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
-# Date created = 23:52:20  November 09, 2021
+# Date created = 13:29:40  November 11, 2021
 #
 # -------------------------------------------------------------------------- #
 #
@@ -52,7 +52,6 @@ set_global_assignment -name QIP_FILE rtl/intel/gpio/intel_gpio_ddro.qip
 set_global_assignment -name QIP_FILE rtl/intel/pll/intel_pll.qip
 set_global_assignment -name SDC_FILE SummerCart64.sdc
 set_global_assignment -name SYSTEMVERILOG_FILE picorv32/picorv32.v
-set_global_assignment -name SYSTEMVERILOG_FILE ../sw/riscv/build/cpu_bootloader.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_bus.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_cfg.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/cpu/cpu_dma.sv
@@ -83,7 +82,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/config.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/sc64.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/system/system.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/usb/usb_ft1248.sv
-set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:scripts/post_flow.tcl"
+set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:scripts/post_module.tcl"
 
 # Pin & Location Assignments
 # ==========================
@@ -289,22 +288,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
 	# -------------------------
 
 # end ENTITY(SummerCart64)
-# ------------------------
-
-# ------------------------------
-# start ENTITY(altera_gpio_lite)
-
-	# Project-Wide Assignments
-	# ========================
-
-# end ENTITY(altera_gpio_lite)
-# ----------------------------
-
-# -----------------------------
-# start ENTITY(intel_gpio_ddro)
-
-	# Project-Wide Assignments
-	# ========================
-
-# end ENTITY(intel_gpio_ddro)
-# ---------------------------
+# ------------------------

fw/rtl/cpu/cpu_soc.sv

@@ -40,9 +40,10 @@ module cpu_soc (
         .bus(bus.at[sc64::ID_CPU_RAM].device)
     );
 
-    cpu_bootloader cpu_bootloader_inst (
+    cpu_flash cpu_flash_inst (
         .sys(sys),
-        .bus(bus.at[sc64::ID_CPU_BOOTLOADER].device)
+        .bus(bus.at[sc64::ID_CPU_FLASH].device),
+        .flash(flash)
     );
 
     cpu_gpio cpu_gpio_inst (
@@ -71,12 +72,16 @@ module cpu_soc (
         .usb_pwren(usb_pwren)
     );
 
-    cpu_uart cpu_uart_inst (
-        .sys(sys),
-        .bus(bus.at[sc64::ID_CPU_UART].device),
-        .uart_rxd(uart_rxd),
-        .uart_txd(uart_txd)
-    );
+    generate
+        if (sc64::CPU_HAS_UART) begin
+            cpu_uart cpu_uart_inst (
+                .sys(sys),
+                .bus(bus.at[sc64::ID_CPU_UART].device),
+                .uart_rxd(uart_rxd),
+                .uart_txd(uart_txd)
+            );
+        end
+    endgenerate
 
     cpu_dma cpu_dma_inst (
         .sys(sys),
@@ -108,12 +113,6 @@ module cpu_soc (
         .si(si)
     );
 
-    cpu_flash cpu_flash_inst (
-        .sys(sys),
-        .bus(bus.at[sc64::ID_CPU_FLASH].device),
-        .flash(flash)
-    );
-
     assign sd_clk = 1'bZ;
     assign sd_cmd = 1'bZ;
     assign sd_dat = 4'bZZZZ;

fw/rtl/cpu/cpu_wrapper.sv

@@ -33,7 +33,7 @@ module cpu_wrapper (
         .ENABLE_COUNTERS64(0),
         .CATCH_MISALIGN(0),
         .CATCH_ILLINSN(0),
-        .PROGADDR_RESET({4'(sc64::ID_CPU_BOOTLOADER), 28'h000_0000})
+        .PROGADDR_RESET(sc64::CPU_RESET_VECTOR)
     ) cpu_inst (
         .clk(sys.clk),
         .resetn(~sys.reset),

fw/rtl/intel/flash/intel_flash.qsys

@@ -6,7 +6,7 @@
    version="1.0"
    description=""
    tags="INTERNAL_COMPONENT=true"
-   categories="" />
+   categories="System" />
  <parameter name="bonusData"><![CDATA[bonusData 
 {
    element onchip_flash_0
@@ -78,10 +78,10 @@
   <parameter name="READ_BURST_MODE" value="Incrementing" />
   <parameter name="SECTOR_ACCESS_MODE">Read and write,Read and write,Hidden,Read and write,Read and write</parameter>
   <parameter name="autoInitializationFileName">$${FILENAME}_onchip_flash_0</parameter>
-  <parameter name="initFlashContent" value="true" />
-  <parameter name="initializationFileName">../sw/n64/build/SummerLoader64.hex</parameter>
-  <parameter name="initializationFileNameForSim">../sw/n64/build/SummerLoader64.hex</parameter>
-  <parameter name="useNonDefaultInitFile" value="true" />
+  <parameter name="initFlashContent" value="false" />
+  <parameter name="initializationFileName"></parameter>
+  <parameter name="initializationFileNameForSim"></parameter>
+  <parameter name="useNonDefaultInitFile" value="false" />
  </module>
  <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
  <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />

fw/rtl/system/sc64.sv

@@ -11,7 +11,7 @@ package sc64;
 
     typedef enum bit [3:0] {
         ID_CPU_RAM,
-        ID_CPU_BOOTLOADER,
+        ID_CPU_FLASH,
         ID_CPU_GPIO,
         ID_CPU_I2C,
         ID_CPU_USB,
@@ -21,7 +21,6 @@ package sc64;
         ID_CPU_SDRAM,
         ID_CPU_FLASHRAM,
         ID_CPU_SI,
-        ID_CPU_FLASH,
         __ID_CPU_END
     } e_cpu_id;
 
@@ -31,10 +30,10 @@ package sc64;
         __ID_DMA_END
     } e_dma_id;
 
-    parameter bit [31:0] SC64_VER   = 32'h53437632;
-
-    parameter int CLOCK_FREQUENCY   = 32'd100_000_000;
-
-    parameter int UART_BAUD_RATE    = 32'd1_000_000;
+    parameter bit [31:0] SC64_VER           = 32'h53437632;
+    parameter int CLOCK_FREQUENCY           = 32'd100_000_000;
+    parameter bit [31:0] CPU_RESET_VECTOR   = {4'(ID_CPU_FLASH), 28'h0035800};
+    parameter bit CPU_HAS_UART              = 1'b0;
+    parameter int UART_BAUD_RATE            = 32'd1_000_000;
 
 endpackage

fw/scripts/post_flow.tcl → fw/scripts/post_module.tcl

@@ -1,6 +1,6 @@
 set flow [lindex $quartus(args) 0]
 
-if [string match "compile" $flow] {
+if [string match "quartus_asm" $flow] {
     post_message "Generating final programming file"
     qexec "quartus_cpf -c SummerCart64.cof"
 }

sw/riscv/Makefile

@@ -1,47 +1,44 @@
 TOOLCHAIN = riscv32-unknown-elf-
 CC = $(TOOLCHAIN)gcc
+AS = $(TOOLCHAIN)as
 OBJCOPY = $(TOOLCHAIN)objcopy
+OBJDUMP = $(TOOLCHAIN)objdump
 SIZE = $(TOOLCHAIN)size
 
-FLAGS = -mabi=ilp32 -march=rv32i $(USER_FLAGS)
+FLAGS = -mabi=ilp32 -march=rv32i
 CFLAGS = -Os -Wall -ffunction-sections -fdata-sections -ffreestanding -MMD -MP
 LDFLAGS = -nostartfiles -Wl,--gc-sections
 
 SRC_DIR = src
 BUILD_DIR = build
 
-SRCS = $(wildcard $(patsubst %, %/*.c, . $(SRC_DIR)))
-OBJS = $(addprefix $(BUILD_DIR)/, $(notdir $(SRCS:.c=.o)))
+SRC_FILES = startup.S process.c usb.c cfg.c dma.c joybus.c rtc.c i2c.c flashram.c uart.c flash.c
+
+SRCS = $(addprefix $(SRC_DIR)/, $(SRC_FILES))
+OBJS = $(addprefix $(BUILD_DIR)/, $(notdir $(patsubst %,%.o,$(SRCS))))
 DEPS = $(OBJS:.o=.d)
 
 VPATH = $(SRC_DIR)
 
 $(@info $(shell mkdir -p ./$(BUILD_DIR) &> /dev/null))
 
-all: $(BUILD_DIR)/cpu_bootloader.sv $(BUILD_DIR)/controller.rom
+all: $(BUILD_DIR)/governor.hex
 
-$(BUILD_DIR)/%.o: %.c
-	$(CC) $(FLAGS) $(CFLAGS) -c $< -o $@
+$(BUILD_DIR)/%.c.o: %.c
+	$(CC) $(FLAGS) $(CFLAGS) $(USER_FLAGS) -c $< -o $@
 
-$(BUILD_DIR)/uc.elf: $(OBJS) SC64.ld
-	$(CC) $(FLAGS) $(LDFLAGS) -TSC64.ld $(OBJS) -o $@
+$(BUILD_DIR)/%.S.o: %.S
+	$(AS) $(FLAGS) $(ASFLAGS) -c $< -o $@
 
-$(BUILD_DIR)/controller.rom: $(BUILD_DIR)/uc.elf
-	$(OBJCOPY) -R .bootloader $(BUILD_DIR)/uc.elf $(BUILD_DIR)/controller.elf
-	$(OBJCOPY) -O binary --set-section-flags .bss=alloc,contents $(BUILD_DIR)/controller.elf $(BUILD_DIR)/controller.bin
-	$(OBJCOPY) -I binary -O ihex $(BUILD_DIR)/controller.bin $(BUILD_DIR)/controller.hex
-	python3 tools/bin2rom.py $@ < $(BUILD_DIR)/controller.bin
-	@echo 'Size of controller modules:'
+$(BUILD_DIR)/governor.hex: $(OBJS) SC64.ld
+	$(CC) $(FLAGS) $(LDFLAGS) -TSC64.ld $(OBJS) -o $(BUILD_DIR)/governor.elf
+	$(OBJDUMP) -D $(BUILD_DIR)/governor.elf > $(BUILD_DIR)/governor.map
+	$(OBJCOPY) -O binary $(BUILD_DIR)/governor.elf $(BUILD_DIR)/governor.bin
+	$(OBJCOPY) -I binary -O ihex $(BUILD_DIR)/governor.bin $@
+	@echo 'Size of modules:'
 	@$(SIZE) -B -t --common $(OBJS)
-	@echo 'Size of controller:'
-	@$(SIZE) -B $(BUILD_DIR)/controller.elf
-
-$(BUILD_DIR)/cpu_bootloader.sv: $(BUILD_DIR)/uc.elf
-	$(OBJCOPY) -j .bootloader $(BUILD_DIR)/uc.elf $(BUILD_DIR)/bootloader.elf
-	$(OBJCOPY) -O binary $(BUILD_DIR)/bootloader.elf $(BUILD_DIR)/bootloader.bin
-	python3 tools/bin2sv.py tools/cpu_bootloader_template.sv $@ < $(BUILD_DIR)/bootloader.bin
-	@echo 'Size of bootloader:'
-	@$(SIZE) -B $(BUILD_DIR)/bootloader.elf
+	@echo 'Size of governor:'
+	@$(SIZE) -B $(BUILD_DIR)/governor.elf
 
 clean:
 	rm -rf ./$(BUILD_DIR)/*