Merge branch 'main' into new-irq

Polprzewodnikowy · May 20, 2024 · e163ae8 · e163ae8
2 parents dea9441 + 6bbfee4
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diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
@@ -147,6 +147,9 @@ jobs:
       - name: Download SummerCart64 repository
         uses: actions/checkout@v4
 
+      - name: Copy BOM file to the website folder
+        run: cp ./hw/pcb/sc64v2_bom.html ./web
+
       - name: Setup GitHub pages
         uses: actions/configure-pages@v4
 

diff --git a/README.md b/README.md
@@ -1,4 +1,4 @@
-# SummerCart64 - a fully open source Nintendo 64 flashcart
+# SummerCart64 - a fully open source N64 flashcart
 [<img src="assets/sc64_logo.svg" />](assets/sc64_logo.svg)
 
 **For non-technical description of the SummerCart64, please head to the https://summercart64.dev website!**
@@ -52,7 +52,7 @@ Note that my time is limited so I can't answer all questions.
 
 Most up to date information about purchasing/manufacturing options is available on https://summercart64.dev website!
 
-If you want to order it yourself then I've prepared all necessary manufacturing files on the [PCBWay Shared Project](https://www.pcbway.com/project/shareproject/SC64_an_open_source_Nintendo_64_flashcart_14b9688a.html) site.
+If you want to order it yourself then I've prepared all necessary manufacturing files on the [PCBWay Shared Project](https://www.pcbway.com/project/member/shareproject/?bmbno=1046ED64-8AEE-44) site.
 
 **Be careful**: this is an advanced project and it is assumed that you have enough knowledge about electronics.
 Selecting wrong options or giving PCB manufacturer wrong information might result in an undesired time and/or money loss.
@@ -61,7 +61,7 @@ Boards also come unprogrammed from the manufacturer - you need to do **initial p
 To avoid problems _**please**_ read **both** [build guide](./docs/06_build_guide.md) and description on the shared project page **in full**.
 If you have even slightest doubt about the ordering or programming process, it is better to leave it to someone experienced - ask in the [n64brew Discord server](https://discord.gg/WqFgNWf) if that's the case.
 
-**Full disclosure**: for every order made through [this link](https://www.pcbway.com/project/shareproject/SC64_an_open_source_Nintendo_64_flashcart_14b9688a.html) I will receive 10% of PCB manufacturing and PCB assembly service cost (price of the components is not included in the split). This is a great way of supporting further project development.
+**Full disclosure**: for every order made through [this link](https://www.pcbway.com/project/member/shareproject/?bmbno=1046ED64-8AEE-44) I will receive 10% of PCB manufacturing and PCB assembly service cost (price of the components is not included in the split). This is a great way of supporting further project development.
 
 If you don't need a physical product but still want to support me then check my [GitHub sponsors](https://github.com/sponsors/Polprzewodnikowy) page.
 
@@ -87,8 +87,10 @@ If you don't need a physical product but still want to support me then check my
 
 This project wouldn't be possible without these contributions:
 
-- [64drive](https://64drive.retroactive.be) orders being on permanent hold long before creating this repository.
+- [64drive](https://64drive.retroactive.be) ([archived](https://web.archive.org/web/20240406215731/https://64drive.retroactive.be/)) orders being on permanent hold long before creating this repository.
 - [EverDrive-64 X7](https://krikzz.com/our-products/cartridges/ed64x7.html) being disappointment for homebrew development (slow USB upload, unjustified price and overcomplicated SD card access).
+  - Context: Both aforementioned products were priced at $199 in 2020. 64drive features made it a vastly more useful tool for homebrew development.
+    Since then, 64drive had never been restocked and EverDrive-64 X7 price was lowered to $159 (as of May 2024).
 - [Jan Goldacker (@jago85)](https://github.com/jago85) and his projects:
   - [Brutzelkarte](https://github.com/jago85/Brutzelkarte_FPGA) providing solid base for starting this project and sparking hope for true open source N64 flashcarts.
   - [UltraCIC_C](https://github.com/jago85/UltraCIC_C) reimplementation for easy integration in modern microcontrollers. Thanks also goes to everyone involved in N64 CIC reverse engineering.

diff --git a/build.sh b/build.sh
@@ -17,7 +17,7 @@ TOP_FILES=(
 FILES=(
     "./assets/*"
     "./docs/*"
-    "./hw/pcb/sc64_hw_v2.0a_bom.html"
+    "./hw/pcb/sc64v2_bom.html"
     "./hw/pcb/sc64v2.kicad_pcb"
     "./hw/pcb/sc64v2.kicad_pro"
     "./hw/pcb/sc64v2.kicad_sch"

diff --git a/docs/06_build_guide.md b/docs/06_build_guide.md
@@ -42,7 +42,7 @@ Please download latest release before proceeding with the instructions.
 
 ### **Components**
 
-  1. Locate interactive BOM file inside `hw/pcb` folder
+  1. Locate interactive BOM file inside `hw/pcb` folder (alternatively, check out this [BOM discussion](https://github.com/Polprzewodnikowy/SummerCart64/discussions/27))
   2. Order all parts listed in the BOM file or use PCB assembly service together with your PCB order
 
 ---
@@ -75,17 +75,19 @@ You will require the following hardware:
  - A USB to UART (serial) adapter (with 3.3V signaling is required, e.g. TTL-232R-3V3).
 
 You will require the following applications and packages:
+ - [Latest FTDI drivers](https://ftdichip.com/drivers/)
  - [FT_PROG](https://ftdichip.com/utilities/#ft_prog) - FTDI FT232H EEPROM programming software.
  - [Python 3](https://www.python.org/downloads/) with `pip3` - necessary for initial programming script: `primer.py` (Windows install: check option add python to PATH).
  - [`sc64-extra-{version}.zip`](https://github.com/Polprzewodnikowy/SummerCart64/releases) - programming scripts and firmware files, download the latest version.
 
 **Programming must be done in specific order for `primer.py` script to work correctly.**
 
 Preparations:
- 1. Install FT_PROG.
- 2. Install Python 3.
- 3. Unpack `sc64-extra-{version}.zip` into a folder.
- 4. Open terminal and navigate to the folder you've unpacked SC64 files.
+ 1. Install latest FTDI drivers (especially on Windows 10).
+ 2. Install FT_PROG.
+ 3. Install Python 3.
+ 4. Unpack `sc64-extra-{version}.zip` into a folder.
+ 5. Open terminal and navigate to the folder you've unpacked SC64 files.
 
 First, program the ***FT232H EEPROM***:
  1. Connect the SC64 board to your PC with a USB-C cable.

diff --git a/docs/README.md b/docs/README.md
@@ -1,4 +1,4 @@
-# SummerCart64 - a fully open source Nintendo 64 flashcart
+# SummerCart64 - a fully open source N64 flashcart
 [<img src="../assets/sc64_logo.svg" />](../assets/sc64_logo.svg)
 
 ## Documentation

diff --git a/fw/project/lcmxo2/sc64.lpf b/fw/project/lcmxo2/sc64.lpf
@@ -96,6 +96,9 @@ IOBUF PORT "sdram_dqm[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
 IOBUF PORT "sdram_dqm[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
 IOBUF PORT "sdram_ras" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
 IOBUF PORT "sdram_we" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "test_point[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "test_point[1]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "test_point[2]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
 IOBUF PORT "usb_clk" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
 IOBUF PORT "usb_cs" PULLMODE=UP IO_TYPE=LVCMOS33 ;
 IOBUF PORT "usb_miosi[0]" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
@@ -194,6 +197,9 @@ LOCATE COMP "sdram_dqm[0]" SITE "97" ;
 LOCATE COMP "sdram_dqm[1]" SITE "73" ;
 LOCATE COMP "sdram_ras" SITE "94" ;
 LOCATE COMP "sdram_we" SITE "96" ;
+LOCATE COMP "test_point[0]" SITE "23" ;
+LOCATE COMP "test_point[1]" SITE "24" ;
+LOCATE COMP "test_point[2]" SITE "25" ;
 LOCATE COMP "usb_clk" SITE "12" ;
 LOCATE COMP "usb_cs" SITE "11" ;
 LOCATE COMP "usb_miosi[0]" SITE "22" ;
@@ -213,3 +219,43 @@ BLOCK PATH TO PORT "mcu_int" ;
 BLOCK PATH TO PORT "n64_irq" ;
 BLOCK PATH FROM PORT "usb_pwrsav" ;
 BLOCK PATH FROM PORT "sd_det" ;
+DEFINE PORT GROUP "sdram_output" "sdram_cs" 
+"sdram_ras" 
+"sdram_cas" 
+"sdram_we" 
+"sdram_ba[1]" 
+"sdram_ba[0]" 
+"sdram_a[12]" 
+"sdram_a[11]" 
+"sdram_a[10]" 
+"sdram_a[9]" 
+"sdram_a[8]" 
+"sdram_a[7]" 
+"sdram_a[6]" 
+"sdram_a[5]" 
+"sdram_a[4]" 
+"sdram_a[3]" 
+"sdram_a[2]" 
+"sdram_a[1]" 
+"sdram_a[0]" 
+"sdram_dqm[1]" 
+"sdram_dqm[0]" ;
+DEFINE PORT GROUP "sdram_bidir" "sdram_dq[15]" 
+"sdram_dq[14]" 
+"sdram_dq[13]" 
+"sdram_dq[12]" 
+"sdram_dq[11]" 
+"sdram_dq[10]" 
+"sdram_dq[9]" 
+"sdram_dq[8]" 
+"sdram_dq[7]" 
+"sdram_dq[6]" 
+"sdram_dq[5]" 
+"sdram_dq[4]" 
+"sdram_dq[3]" 
+"sdram_dq[2]" 
+"sdram_dq[1]" 
+"sdram_dq[0]" ;
+INPUT_SETUP GROUP "sdram_bidir"INPUT_DELAY 5.400000 ns HOLD -2.500000 ns CLKNET "clk" CLK_OFFSET -0.250000 X ;
+CLOCK_TO_OUT GROUP "sdram_output" OUTPUT_DELAY 1.500000 ns MIN 0.800000 ns CLKNET "clk" CLKOUT PORT "sdram_clk" ;
+CLOCK_TO_OUT GROUP "sdram_bidir" OUTPUT_DELAY 1.500000 ns MIN 0.800000 ns CLKNET "clk" CLKOUT PORT "sdram_clk" ;
diff --git a/fw/rtl/memory/memory_flash.sv b/fw/rtl/memory/memory_flash.sv
@@ -234,7 +234,7 @@ module memory_flash (
         if (reset) begin
             state <= STATE_IDLE;
         end else begin
-            if (!busy && (start || finish)) begin
+            if ((start || finish) && !busy) begin
                 counter <= counter + 1'd1;
             end
 
@@ -248,6 +248,7 @@ module memory_flash (
                     end else if (mem_bus.request) begin
                         current_address <= {mem_bus.address[23:1], 1'b0};
                         if (mem_bus.write) begin
+                            current_address[0] <= (~mem_bus.wmask[1]);
                             state <= STATE_WRITE_ENABLE;
                         end else begin
                             state <= STATE_READ_START;
@@ -263,7 +264,7 @@ module memory_flash (
                         end
                         3'd1: begin
                             finish <= 1'b1;
-                            wdata <= 8'd4;
+                            wdata <= 8'd5;
                             if (!busy) begin
                                 counter <= 3'd0;
                                 if (flash_scb.erase_pending) begin
@@ -296,7 +297,7 @@ module memory_flash (
                         end
                         3'd4: begin
                             finish <= 1'b1;
-                            wdata <= 8'd4;
+                            wdata <= 8'd5;
                             if (!busy) begin
                                 flash_scb.erase_done <= 1'b1;
                                 counter <= 3'd0;
@@ -314,17 +315,17 @@ module memory_flash (
                         end
                         3'd1: begin
                             start <= 1'b1;
-                            wdata <= mem_bus.address[23:16];
+                            wdata <= current_address[23:16];
                         end
                         3'd2: begin
                             start <= 1'b1;
-                            wdata <= mem_bus.address[15:8];
+                            wdata <= current_address[15:8];
                         end
                         3'd3: begin
                             start <= 1'b1;
-                            wdata <= mem_bus.address[7:0];
+                            wdata <= current_address[7:0];
                             if (!busy) begin
-                                counter <= 3'd0;
+                                counter <= 3'd0 + current_address[0];
                                 state <= STATE_PROGRAM;
                             end
                         end
@@ -336,35 +337,42 @@ module memory_flash (
                         3'd0: begin
                             start <= 1'b1;
                             wdata <= mem_bus.wdata[15:8];
+                            if (start && !busy) begin
+                                current_address <= current_address + 1'd1;
+                                if (!mem_bus.wmask[0]) begin
+                                    counter <= 3'd2;
+                                    mem_bus.ack <= 1'b1;
+                                end
+                            end
                         end
                         3'd1: begin
                             start <= 1'b1;
                             wdata <= mem_bus.wdata[7:0];
                             if (!busy) begin
                                 mem_bus.ack <= 1'b1;
-                                current_address <= current_address + 2'd2;
+                                current_address <= current_address + 1'd1;
                             end
                         end
                         3'd2: begin
                             if (current_address[7:0] == 8'h00) begin
                                 state <= STATE_PROGRAM_END;
-                            end else if (flash_scb.erase_pending) begin
-                                state <= STATE_PROGRAM_END;
                             end else if (mem_bus.request && !mem_bus.ack) begin
-                                if (!mem_bus.write || (mem_bus.address[23:0] != current_address)) begin
-                                    state <= STATE_PROGRAM_END;
-                                end else begin
+                                if (mem_bus.write && mem_bus.wmask[1] && (mem_bus.address[23:0] == current_address)) begin
                                     counter <= 3'd0;
+                                end else begin
+                                    state <= STATE_PROGRAM_END;
                                 end
+                            end else if (!busy) begin
+                                state <= STATE_PROGRAM_END;
                             end
                         end
                     endcase
                 end
 
                 STATE_PROGRAM_END: begin
                     finish <= 1'b1;
-                    wdata <= 8'd4;
-                    if (!busy) begin
+                    wdata <= 8'd5;
+                    if (finish && !busy) begin
                         counter <= 3'd0;
                         state <= STATE_WAIT;
                     end
@@ -407,15 +415,15 @@ module memory_flash (
                         3'd1: begin
                             start <= 1'b1;
                             quad_enable <= 1'b1;
-                            wdata <= mem_bus.address[23:16];
+                            wdata <= current_address[23:16];
                         end
                         3'd2: begin
                             start <= 1'b1;
-                            wdata <= mem_bus.address[15:8];
+                            wdata <= current_address[15:8];
                         end
                         3'd3: begin
                             start <= 1'b1;
-                            wdata <= mem_bus.address[7:0];
+                            wdata <= current_address[7:0];
                         end
                         3'd4: begin
                             start <= 1'b1;

diff --git a/fw/rtl/n64/n64_cic.sv b/fw/rtl/n64/n64_cic.sv
@@ -37,8 +37,13 @@ module n64_cic (
     end
 
     logic cic_dq_out;
+    logic cic_dq_oe;
 
-    assign n64_cic_dq = cic_dq_out ? 1'bZ : 1'b0;
+    always_ff @(posedge clk) begin
+        cic_dq_oe <= ~cic_dq_out;
+    end
+
+    assign n64_cic_dq = cic_dq_oe ? 1'b0 : 1'bZ;
 
 
     // Timer (divider and counter)

diff --git a/fw/rtl/top.sv b/fw/rtl/top.sv
@@ -51,7 +51,10 @@ module top (
     output mcu_miso,
 
     // Unused I/O
-    output n64_video_sync
+
+    output n64_video_sync,
+
+    output [2:0] test_point
 );
 
     logic clk;
@@ -278,4 +281,6 @@ module top (
 
     assign n64_video_sync = 1'bZ;
 
+    assign test_point = 3'b000;
+
 endmodule
diff --git a/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v b/fw/rtl/vendor/lcmxo2/generated/pll_lattice_generated.v
diff --git a/fw/rtl/vendor/lcmxo2/pll.sv b/fw/rtl/vendor/lcmxo2/pll.sv
@@ -17,8 +17,8 @@ module pll (
     );
 
     ODDRXE oddrxe_sdram_clk_inst (
-        .D0(1'b0),
-        .D1(1'b1),
+        .D0(1'b1),
+        .D1(1'b0),
         .SCLK(pll_sdram_clk),
         .RST(1'b0),
         .Q(buf_sdram_clk)