Test

.wordlist.txt

@@ -7,16 +7,19 @@ APUs
 AQL
 AXPY
 asm
-Asynchrony
+asynchrony
 backtrace
 Bitcode
 bitcode
 bitcodes
+blockDim
+blockIdx
 builtins
 Builtins
 CAS
 clr
 compilable
+constexpr
 coroutines
 Ctx
 cuBLASLt
@@ -51,6 +54,7 @@ FNUZ
 fp
 gedit
 GPGPU
+gridDim
 GROMACS
 GWS
 hardcoded
@@ -87,6 +91,7 @@ iteratively
 Lapack
 latencies
 libc
+libhipcxx
 libstdc
 lifecycle
 linearizing
@@ -97,6 +102,7 @@ makefile
 Malloc
 malloc
 MALU
+maxregcount
 MiB
 memset
 multicore
@@ -118,13 +124,15 @@ overindexing
 oversubscription
 overutilized
 parallelizable
+parallelized
 pixelated
 pragmas
 preallocated
 preconditioners
 predefining
 prefetched
 preprocessor
+printf
 profilers
 PTX
 PyHIP
@@ -153,6 +161,7 @@ SYCL
 syntaxes
 texel
 texels
+threadIdx
 tradeoffs
 templated
 toolkits
@@ -167,5 +176,6 @@ unregister
 upscaled
 variadic
 vulkan
+warpSize
 WinGDB
 zc

README.md

@@ -12,6 +12,9 @@ Key features include:
 
 New projects can be developed directly in the portable HIP C++ language and can run on either NVIDIA or AMD platforms.  Additionally, HIP provides porting tools which make it easy to port existing CUDA codes to the HIP layer, with no loss of performance as compared to the original CUDA application.  HIP is not intended to be a drop-in replacement for CUDA, and developers should expect to do some manual coding and performance tuning work to complete the port.
 
+> [!NOTE]
+> The published documentation is available at [HIP documentation](https://rocm.docs.amd.com/projects/HIP/en/latest/index.html) in an organized, easy-to-read format, with search and a table of contents. The documentation source files reside in the `HIP/docs` folder of this GitHub repository. As with all ROCm projects, the documentation is open source. For more information on contributing to the documentation, see [Contribute to ROCm documentation](https://rocm.docs.amd.com/en/latest/contribute/contributing.html).
+
 ## DISCLAIMER
 
 The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions, and typographical errors. The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to product and roadmap changes, component and motherboard versionchanges, new model and/or product releases, product differences between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. Any computer system has risks of security vulnerabilities that cannot be completely prevented or mitigated.AMD assumes no obligation to update or otherwise correct or revise this information. However, AMD reserves the right to revise this information and to make changes from time to time to the content hereof without obligation of AMD to notify any person of such revisions or changes.THIS INFORMATION IS PROVIDED ‘AS IS.” AMD MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE CONTENTS HEREOF AND ASSUMES NO RESPONSIBILITY FOR ANY INACCURACIES, ERRORS, OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION. AMD SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO EVENT WILL AMD BE LIABLE TO ANY PERSON FOR ANY RELIANCE, DIRECT, INDIRECT, SPECIAL, OR OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF AMD IS EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. AMD, the AMD Arrow logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.