More Attiny817 support

Makefile

@@ -34,7 +34,7 @@ svd/%.svd.patched: svd/%.svd .deps/%.d
 src/devices/%/mod.full.rs: svd/%.svd.patched
 	@mkdir -p $(@D)
 	@echo -e "\tSVD2RUST\t$*"
-	@cd $(@D); svd2rust --generic_mod --make_mod --target none -i $(realpath $<)
+	@cd $(@D); svd2rust --generic_mod --make_mod --target avr -i $(realpath $<)
 	@mv $(@D)/mod.rs $@
 	@mv $(@D)/generic.rs $(@D)/../../generic.rs
 

patch/attiny817.yaml

@@ -1 +1,99 @@
 _svd: ../svd/attiny817.svd
+
+CRCSCAN:
+  CTRLB:
+    SRC:
+      _replace_enum:
+        FLASH: [0, "CRC on entire flash"]
+        BOOTAPP: [1, "CRC on boot and appl section of flash"]
+        BOOT: [2, "CRC on boot section of flash"]
+    MODE:
+      _replace_enum:
+        PRIORITY: [0, "Priority to flash"]
+
+NVMCTRL:
+  CTRLA:
+    CMD:
+      _replace_enum:
+        NONE: [0, "No command"]
+        WP: [1, "Write page"]
+        ER: [2, "Erase page"]
+        ERWP: [3, "Erase and write page"]
+        PBC: [4, "Page buffer clear"]
+        CHER: [5, "Chip erase"]
+        EEER: [6, "EEPROM erase"]
+        WFU: [7, "Write fuse (PDI only)"]
+
+SLPCTRL:
+  CTRLA:
+    SMODE:
+      _replace_enum:
+        IDLE: [0, "Idle mode"]
+        STANDBY: [1, "Standby Mode"]
+        PDOWN: [2, "Power-down Mode"]
+
+TCD0:
+  EVCTRL?:
+    CFG:
+      _replace_enum:
+        NEITHER: [0, "Neither Filter nor Asynchronous Event is enabled"]
+        FILTERON: [1, "Input Capture Noise Cancellation Filter enabled"]
+        ASYNCON: [2, "Asynchronous Event output qualification enabled"]
+
+"PORT?":
+  DIR:
+    "P*":
+      # Make all Pins use the same enum
+      _replace_enum:
+        Input: [0, "Input"]
+        Output: [1, "Output"]
+
+  # make PINxCTRL a rust slice
+  _array:
+    "PIN?CTRL": {}
+
+"USART?":
+  STATUS:
+    _modify:
+      # The RXSIF bit is actually writable to clear the flag
+      RXSIF:
+        access: read-write
+      # The WFB bit is write-only
+      WFB:
+        access: write-only
+
+"SPI?":
+  CTRLA:
+    DORD:
+      # Make it an enum
+      _replace_enum:
+        MsbFirst: [0, "Most significant byte first"]
+        LsbFirst: [1, "Least significant byte first"]
+
+CCL:
+  _cluster:
+    "LUT%s":
+      description: "CCL LUT configuration cluster"
+      "LUT?CTRLA": {}
+      "LUT?CTRLB": {}
+      "LUT?CTRLC": {}
+      "TRUTH?": {}
+
+  # turn all SEQCTRL-registers into slices
+  _array:
+    "SEQCTRL?": {}
+
+CPUINT:
+  CTRLA:
+    IVSEL:
+      _replace_enum:
+        AFTERBOOT: [0, "Interrupt vectors are placed after the BOOT section of the Flash"]
+        INBOOT: [1, "Interrupt vectors are placed at the start of the BOOT section of the Flash"]
+    CVT:
+      _replace_enum:
+        NORMAL: [0, "Compact Vector Table function is disabled"]
+        COMPACT: [1, "Compact Vector Table function is enabled"]
+    LVL0RR:
+      _replace_enum:
+        FIXED: [0, "Priority is fixed for priority level 0 interrupt requests: The lowest interrupt vector address has the highest priority."]
+        ROUNDROBIN: [1, "The round robin priority scheme is enabled for priority level 0 interrupt requests"]

src/ccp.rs

@@ -0,0 +1,41 @@
+//! Configuration change protected (CCP) register definitions
+
+pub use crate::generic::ProtectedWritable;
+
+#[cfg(feature = "attiny817")]
+pub mod attiny817 {
+    use crate::generic::{UnlockRegister, Protected};
+
+    // Mark the CPU.CCP register with the UnlockRegister trait so that it can be used to unlock the below defined registers
+    impl UnlockRegister for crate::attiny817::cpu::ccp::CCP_SPEC { const PTR: *mut u8 = 0x34 as *mut u8; }
+
+    // Configuration change protected registers in NVMCTRL
+    impl Protected for crate::attiny817::nvmctrl::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0x9D; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::nvmctrl::ctrlb::CTRLB_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+
+    // Configuration change protected registers in CLKCTRL
+    impl Protected for crate::attiny817::clkctrl::mclkctrlb::MCLKCTRLB_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::mclklock::MCLKLOCK_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::xosc32kctrla::XOSC32KCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::mclkctrla::MCLKCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::osc20mctrla::OSC20MCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::osc20mcaliba::OSC20MCALIBA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::osc20mcalibb::OSC20MCALIBB_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::clkctrl::osc32kctrla::OSC32KCTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+
+    // Configuration change protected registers in RSTCTRL
+    impl Protected for crate::attiny817::rstctrl::swrr::SWRR_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+
+    // Configuration change protected registers in CPUINT
+    impl Protected for crate::attiny817::cpuint::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+
+    // Configuration change protected registers in BOD
+    impl Protected for crate::attiny817::bod::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+
+    // Configuration change protected registers in WDT
+    impl Protected for crate::attiny817::wdt::ctrla::CTRLA_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+    impl Protected for crate::attiny817::wdt::status::STATUS_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+
+    // Configuration change protected registers in TCD0
+    impl Protected for crate::attiny817::tcd0::faultctrl::FAULTCTRL_SPEC { const MAGIC: u8 = 0xD8; type CcpReg = crate::attiny817::cpu::ccp::CCP_SPEC; }
+}

src/lib.rs

@@ -1,4 +1,5 @@
 //! This crate contains register definitions for
+#![feature(asm_const)]
 
 #![cfg_attr(feature = "at90usb1286", doc = "**at90usb1286**,")]
 #![cfg_attr(feature = "atmega1280", doc = "**atmega1280**,")]
@@ -320,3 +321,9 @@ pub use crate::devices::attiny85;
 pub use crate::devices::attiny861;
 #[cfg(feature = "attiny88")]
 pub use crate::devices::attiny88;
+
+#[allow(non_camel_case_types, unused_attributes, unreachable_patterns)]
+pub mod ccp;
+
+#[cfg(feature = "attiny817")]
+pub use crate::ccp::attiny817 as attiny817_ccp;