Made mostly using combinational logic
The following instructtions are implemented
- add
- sub
- xor
- or
- and
- sll
- srl
- sra
- slt
- sltu
- lw
- sw
-
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Verilog implementation of a RISC-V processor with a subset of RISC-V instructions
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Shiva9361/Simple_Processor
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Verilog implementation of a RISC-V processor with a subset of RISC-V instructions
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