-
Notifications
You must be signed in to change notification settings - Fork 16
Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Create compatibility module with tests
Signed-off-by: Robert Winkler <[email protected]>
- Loading branch information
Showing
7 changed files
with
194 additions
and
11 deletions.
There are no files selected for viewing
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,63 @@ | ||
#!/usr/bin/env python | ||
# -*- coding: utf-8 -*- | ||
# | ||
# Copyright (C) 2020 The SymbiFlow Authors. | ||
# | ||
# Licensed under the Apache License, Version 2.0 (the "License"); | ||
# you may not use this file except in compliance with the License. | ||
# You may obtain a copy of the License at | ||
# | ||
# https://www.apache.org/licenses/LICENSE-2.0 | ||
# | ||
# Unless required by applicable law or agreed to in writing, software | ||
# distributed under the License is distributed on an "AS IS" BASIS, | ||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
# See the License for the specific language governing permissions and | ||
# limitations under the License. | ||
# | ||
# SPDX-License-Identifier: Apache-2.0 | ||
|
||
import sys | ||
from os import path | ||
|
||
from setuptools import setup, find_packages | ||
|
||
__dir__ = path.dirname(path.abspath(__file__)) | ||
readme_file = path.join(__dir__, '../README.rst') | ||
try: | ||
with open(readme_file) as f: | ||
readme = f.read() | ||
except FileNotFoundError as e: | ||
import traceback | ||
traceback.print_exc() | ||
readme = '' | ||
__version__ = 'error' | ||
|
||
install_requires = [ | ||
'sphinxcontrib-hdl-diagrams' | ||
] | ||
|
||
setup( | ||
name='sphinxcontrib-verilog-diagrams', | ||
version="0.1.0", | ||
description='Generate diagrams from Verilog in Sphinx.', | ||
long_description=readme, | ||
long_description_content_type="text/x-rst", | ||
author="The SymbiFlow Authors", | ||
author_email='[email protected]', | ||
url='https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams', | ||
packages=find_packages(), | ||
license="Apache 2.0", | ||
keywords='Verilog sphinx sphinx-extension netlistsvg FPGA', | ||
classifiers=[ | ||
'Development Status :: 4 - Beta', | ||
'Framework :: Sphinx :: Extension', | ||
'Intended Audience :: Developers', | ||
'License :: OSI Approved :: Apache Software License', | ||
'Natural Language :: English', | ||
'Programming Language :: Python :: 3.5', | ||
'Programming Language :: Python :: 3.6', | ||
'Topic :: Text Processing', | ||
], | ||
install_requires=install_requires, | ||
) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,11 @@ | ||
import sphinxcontrib_hdl_diagrams | ||
|
||
def setup(app): | ||
print("") | ||
print("WARNING:") | ||
print(" sphinxcontrib-verilog-diagram extension is depreciated!") | ||
print(" Please use sphinxcontrib-hdl-diagrams instead:") | ||
print(" https://github.com/SymbiFlow/sphinxcontrib-hdl-diagrams") | ||
print("") | ||
|
||
return sphinxcontrib_hdl_diagrams.setup(app) |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
|
@@ -16,3 +16,4 @@ dependencies: | |
- -r file:requirements.txt | ||
- -r file:docs/requirements.txt | ||
- . | ||
- compat/. |
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,50 @@ | ||
Test Compatibility Package | ||
========================== | ||
|
||
This test checks whether the ``sphinxcontrib-verilog-diagrams`` compatibility | ||
package works as intended. | ||
|
||
Here is the fragment of the ``conf.py`` script, used to configure the extension:: | ||
|
||
extensions = [ | ||
'sphinxcontrib_verilog_diagrams', | ||
] | ||
|
||
Yosys BlackBox Diagram | ||
---------------------- | ||
|
||
.. code-block:: rst | ||
.. verilog-diagram:: adder.v | ||
:type: yosys-blackbox | ||
:module: ADDER | ||
.. verilog-diagram:: adder.v | ||
:type: yosys-blackbox | ||
:module: ADDER | ||
|
||
Yosys AIG Diagram | ||
----------------- | ||
|
||
.. code-block:: rst | ||
.. verilog-diagram:: adder.v | ||
:type: yosys-aig | ||
:module: ADDER | ||
.. verilog-diagram:: adder.v | ||
:type: yosys-aig | ||
:module: ADDER | ||
|
||
Netlistsvg Diagram | ||
------------------ | ||
|
||
.. code-block:: rst | ||
.. verilog-diagram:: adder.v | ||
:type: netlistsvg | ||
:module: ADDER | ||
.. verilog-diagram:: adder.v | ||
:type: netlistsvg | ||
:module: ADDER |