Update variable names after rebasing extension

Signed-off-by: Robert Winkler <[email protected]>
SymbiFlow · Sep 14, 2020 · 15680ee · 15680ee
1 parent dedb7aa
commit 15680ee
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Showing 3 changed files with 38 additions and 38 deletions.
diff --git a/sphinxcontrib_hdl_diagrams/__init__.py b/sphinxcontrib_hdl_diagrams/__init__.py
@@ -162,10 +162,10 @@ class HDLDiagram(Directive):
     }
 
     global_variable_options = {
-        "verilog_diagram_output_format": ["svg", "png"],
-        "verilog_diagram_skin": ["default"],  # or path
-        "verilog_diagram_yosys_script": ["default"],  # or path
-        "verilog_diagram_yosys": ["yowasp", "system"]  # or path
+        "hdl_diagram_output_format": ["svg", "png"],
+        "hdl_diagram_skin": ["default"],  # or path
+        "hdl_diagram_yosys_script": ["default"],  # or path
+        "hdl_diagram_yosys": ["yowasp", "system"]  # or path
     }
 
     def run(self):
@@ -213,7 +213,7 @@ def run(self):
         if yosys_script not in [None, 'default']:
             _, yosys_script_filename = env.relfn2path(yosys_script)
             if not path.exists(yosys_script_filename):
-                raise VerilogDiagramError("Yosys script {} does not exist!".format(yosys_script_filename))
+                raise HDLDiagramError("Yosys script {} does not exist!".format(yosys_script_filename))
             else:
                 node['options']['yosys_script'] = yosys_script_filename
         else:
@@ -223,7 +223,7 @@ def run(self):
         if skin not in [None, 'default']:
             _, skin_filename = env.relfn2path(skin)
             if not os.path.exists(skin_filename):
-                raise VerilogDiagramError("Skin file {} does not exist!".format(skin_filename))
+                raise HDLDiagramError("Skin file {} does not exist!".format(skin_filename))
             else:
                 node['options']['skin'] = skin_filename
         else:
@@ -260,8 +260,8 @@ def diagram_yosys(ipath, opath, module='top', flatten=False,
 
     assert path.exists(ipath), 'Input file missing: {}'.format(ipath)
     assert not path.exists(opath), 'Output file exists: {}'.format(opath)
-    yosys_options = VerilogDiagram.global_variable_options["verilog_diagram_yosys"]
-    assert yosys in yosys_options or os.path.exists(yosys), "Invalid verilog_diagram_yosys value!"
+    yosys_options = HDLDiagram.global_variable_options["hdl_diagram_yosys"]
+    assert yosys in yosys_options or os.path.exists(yosys), "Invalid hdl_diagram_yosys value!"
     if yosys_script != 'default':
         assert path.exists(yosys_script), 'Yosys script file missing: {}'.format(yosys_script)
     oprefix, oext = path.splitext(opath)
@@ -297,7 +297,7 @@ def diagram_yosys(ipath, opath, module='top', flatten=False,
         with open("{}.svg".format(oprefix), "wb") as img:
             img.write(svgdata)
 
-    assert path.exists(opath), 'Output file {} was not created!'.format(oopath)
+    assert path.exists(opath), 'Output file {} was not created!'.format(opath)
     print('Output file created: {}'.format(opath))
 
 def run_netlistsvg(ipath, opath, skin='default'):
@@ -323,8 +323,8 @@ def diagram_netlistsvg(ipath, opath, module='top', flatten=False,
 
     assert path.exists(ipath), 'Input file missing: {}'.format(ipath)
     assert not path.exists(opath), 'Output file exists: {}'.format(opath)
-    yosys_options = VerilogDiagram.global_variable_options["verilog_diagram_yosys"]
-    assert yosys in yosys_options or os.path.exists(yosys), "Invalid verilog_diagram_yosys value!"
+    yosys_options = HDLDiagram.global_variable_options["hdl_diagram_yosys"]
+    assert yosys in yosys_options or os.path.exists(yosys), "Invalid hdl_diagram_yosys value!"
     if yosys_script != 'default':
         assert path.exists(yosys_script), 'Yosys script file missing: {}'.format(yosys_script)
     if skin != 'default':
@@ -366,7 +366,7 @@ def diagram_netlistsvg(ipath, opath, module='top', flatten=False,
 
 def nmigen_to_rtlil(fname, oname):
     subprocess.run([sys.executable, fname], stdout=open(oname, "w"),
-                    shell=False, check=True)
+                   shell=False, check=True)
 
 
 def render_diagram(self, code, options, format, skin, yosys_script):
@@ -389,7 +389,7 @@ def render_diagram(self, code, options, format, skin, yosys_script):
         module = options['module']
     else:
         raise HDLDiagramError("hdl_diagram_code file extension must be one of '.v', "
-                            "'.il', or '.py', but is %r" % source_ext)
+                              "'.il', or '.py', but is %r" % source_ext)
 
     if path.isfile(outfn):
         print('Exiting file:', outfn)
@@ -400,35 +400,35 @@ def render_diagram(self, code, options, format, skin, yosys_script):
     yosys_script = options['yosys_script'] if options['yosys_script'] is not None else yosys_script
     skin = options['skin'] if options['skin'] is not None else skin
 
-    yosys = self.builder.config.verilog_diagram_yosys
-    yosys_options = VerilogDiagram.global_variable_options["verilog_diagram_yosys"]
+    yosys = self.builder.config.hdl_diagram_yosys
+    yosys_options = HDLDiagram.global_variable_options["hdl_diagram_yosys"]
     if yosys not in yosys_options and not os.path.exists(yosys):
-        raise VerilogDiagramError("Yosys not found!")
+        raise HDLDiagramError("Yosys not found!")
     else:
         yosys = yosys if yosys in yosys_options else os.path.realpath(yosys)
 
     diagram_type = options['type']
     if diagram_type.startswith('yosys'):
         assert diagram_type.startswith('yosys-'), diagram_type
         diagram_yosys(
-            verilog_path,
+            source_path,
             outfn,
             module=options['module'],
             flatten=options['flatten'],
             yosys_script=yosys_script,
             yosys=yosys)
     elif diagram_type == 'netlistsvg':
         diagram_netlistsvg(
-            verilog_path,
+            source_path,
             outfn,
             module=options['module'],
             flatten=options['flatten'],
             skin=skin,
             yosys=yosys)
     else:
         raise Exception('Invalid diagram type "%s"' % diagram_type)
-        #raise self.severe(\n' %
-        #                  (SafeString(diagram_type),))
+        # raise self.severe(\n' %
+        #                   (SafeString(diagram_type),))
 
     return relfn, outfn
 
@@ -437,19 +437,19 @@ def render_diagram_html(
         self, node, code, options, imgcls=None, alt=None):
     # type: (nodes.NodeVisitor, hdl_diagram, unicode, Dict, unicode, unicode, unicode) -> Tuple[unicode, unicode]  # NOQA
 
-    yosys_script = self.builder.config.verilog_diagram_yosys_script
+    yosys_script = self.builder.config.hdl_diagram_yosys_script
     if yosys_script != 'default' and not path.exists(yosys_script):
-        raise VerilogDiagramError("Yosys script file {} does not exist! Change verilog_diagram_yosys_script variable".format(yosys_script))
+        raise HDLDiagramError("Yosys script file {} does not exist! Change hdl_diagram_yosys_script variable".format(yosys_script))
 
-    skin = self.builder.config.verilog_diagram_skin
+    skin = self.builder.config.hdl_diagram_skin
     if skin != 'default' and not path.exists(skin):
-        raise VerilogDiagramError("Skin file {} does not exist! Change verilog_diagram_skin variable".format(skin))
+        raise HDLDiagramError("Skin file {} does not exist! Change hdl_diagram_skin variable".format(skin))
 
-    format = self.builder.config.verilog_diagram_output_format
+    format = self.builder.config.hdl_diagram_output_format
     try:
         if format not in ('png', 'svg'):
             raise HDLDiagramError("hdl_diagram_output_format must be one of 'png', "
-                                "'svg', but is %r" % format)
+                                  "'svg', but is %r" % format)
         fname, outfn = render_diagram(self, code, options, format, skin, yosys_script)
     except HDLDiagramError as exc:
         logger.warning('hdl_diagram code %r: ' % code + str(exc))

diff --git a/tests/conf.py.template b/tests/conf.py.template
@@ -13,7 +13,7 @@
 import os
 import sys
 
-sys.path.insert(0, {{ verilog_diagrams_path }})
+sys.path.insert(0, {{ hdl_diagrams_path }})
 
 # -- Project information -----------------------------------------------------
 
@@ -31,7 +31,7 @@ release = '0.1'
 # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
 # ones.
 extensions = [
-    'sphinxcontrib_verilog_diagrams',
+    'sphinxcontrib_hdl_diagrams',
 ]
 
 # Add any paths that contain templates here, relative to this directory.

diff --git a/tests/test.py b/tests/test.py
@@ -8,7 +8,7 @@
 from sphinx.application import Sphinx
 from sphinx.util.docutils import docutils_namespace
 
-VERILOG_DIAGRAMS_PATH = os.path.abspath("..")
+HDL_DIAGRAMS_PATH = os.path.abspath("..")
 
 ## Helpers
 
@@ -75,9 +75,9 @@ def test_netlistsvg_diagram(self):
             "verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
-            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
             "master_doc": "'test_skins'",
-            "custom_variables": "verilog_diagram_skin = os.path.realpath('skin-purple.svg')"
+            "custom_variables": "hdl_diagram_skin = os.path.realpath('skin-purple.svg')"
         }
 
         self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
@@ -104,9 +104,9 @@ def test_yosys_script(self):
             "verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
-            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
             "master_doc": "'test_yosys_script'",
-            "custom_variables": "verilog_diagram_yosys_script = os.path.realpath('yosys_script.ys')"
+            "custom_variables": "hdl_diagram_yosys_script = os.path.realpath('yosys_script.ys')"
         }
 
         self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
@@ -130,7 +130,7 @@ def test_yosys_yowasp(self):
             "verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
-            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
             "master_doc": "'test_yosys_yowasp'",
             "custom_variables": ""
         }
@@ -152,9 +152,9 @@ def test_yosys_system(self):
             "verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
-            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
             "master_doc": "'test_yosys_system'",
-            "custom_variables": "verilog_diagram_yosys = 'system'"
+            "custom_variables": "hdl_diagram_yosys = 'system'"
         }
 
         self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
@@ -177,9 +177,9 @@ def test_yosys_path(self):
         yosys_path = shutil.which("yosys")
 
         TEST_JINJA_DICT = {
-            "verilog_diagrams_path": "'{}'".format(VERILOG_DIAGRAMS_PATH),
+            "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
             "master_doc": "'test_yosys_path'",
-            "custom_variables": "verilog_diagram_yosys = '{}'".format(yosys_path)
+            "custom_variables": "hdl_diagram_yosys = '{}'".format(yosys_path)
         }
 
         self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)