Add tests for RTLIL and nMigen input formats

Signed-off-by: Robert Winkler <[email protected]>
SymbiFlow · Sep 14, 2020 · 33acd3a · 33acd3a
1 parent 79defb4
commit 33acd3a
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Showing 7 changed files with 208 additions and 5 deletions.
diff --git a/.travis.yml b/.travis.yml
@@ -26,6 +26,16 @@ jobs:
       script:
         - cd tests && python3 -m unittest test.TestYosysType
 
+    - stage: Tests
+      name: "Test nMigen input format"
+      script:
+        - cd tests && python3 -m unittest test.TestNMigen
+
+    - stage: Tests
+      name: "Test RTLIL input format"
+      script:
+        - cd tests && python3 -m unittest test.TestRTLIL
+
     - stage: Build
       name: "Build"
       script:

diff --git a/tests/code/nmigen/counter.py b/tests/code/nmigen/counter.py
@@ -0,0 +1,18 @@
+from nmigen import *
+from nmigen.back import rtlil
+
+
+class Counter(Elaboratable):
+    def __init__(self, width):
+        self.v = Signal(width, reset=2**width-1)
+        self.o = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+        m.d.sync += self.v.eq(self.v + 1)
+        m.d.comb += self.o.eq(self.v[-1])
+        return m
+
+
+ctr = Counter(width=16)
+print(rtlil.convert(ctr, ports=[ctr.o]))
diff --git a/tests/code/rtlil/counter.il b/tests/code/rtlil/counter.il
@@ -0,0 +1,49 @@
+attribute \generator "nMigen"
+attribute \top 1
+attribute \nmigen.hierarchy "top"
+module \top
+  attribute \src "counter.py:9"
+  wire width 1 output 0 \o
+  attribute \src "/usr/local/lib/python3.7/site-packages/nmigen/hdl/ir.py:526"
+  wire width 1 input 1 \clk
+  attribute \src "/usr/local/lib/python3.7/site-packages/nmigen/hdl/ir.py:526"
+  wire width 1 input 2 \rst
+  attribute \src "counter.py:8"
+  wire width 16 \v
+  attribute \src "counter.py:8"
+  wire width 16 \v$next
+  attribute \src "counter.py:13"
+  wire width 17 $1
+  attribute \src "counter.py:13"
+  wire width 17 $2
+  attribute \src "counter.py:13"
+  cell $add $3
+    parameter \A_SIGNED 1'0
+    parameter \A_WIDTH 5'10000
+    parameter \B_SIGNED 1'0
+    parameter \B_WIDTH 1'1
+    parameter \Y_WIDTH 5'10001
+    connect \A \v
+    connect \B 1'1
+    connect \Y $2
+  end
+  connect $1 $2
+  process $group_0
+    assign \v$next \v
+    assign \v$next $1 [15:0]
+    attribute \src "/usr/local/lib/python3.7/site-packages/nmigen/hdl/xfrm.py:530"
+    switch \rst
+      case 1'1
+        assign \v$next 16'1111111111111111
+    end
+    sync init
+      update \v 16'1111111111111111
+    sync posedge \clk
+      update \v \v$next
+  end
+  process $group_1
+    assign \o 1'0
+    assign \o \v [15]
+    sync init
+  end
+end
diff --git a/tests/verilog/adder.v → tests/code/verilog/adder.v b/tests/verilog/adder.v → tests/code/verilog/adder.v
diff --git a/tests/test.py b/tests/test.py
@@ -72,7 +72,7 @@ def test_netlistsvg_diagram(self):
             "test_skins/test_skins.rst",
             "test_skins/skin-purple.svg",
             "test_skins/skin-yellow.svg",
-            "verilog/adder.v"
+            "code/verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
             "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
@@ -101,7 +101,7 @@ def test_yosys_script(self):
             "test_yosys_script/test_yosys_script.rst",
             "test_yosys_script/yosys_script.ys",
             "test_yosys_script/yosys_script2.ys",
-            "verilog/adder.v"
+            "code/verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
             "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
@@ -127,7 +127,7 @@ def test_yosys_yowasp(self):
         TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
         TEST_FILES = [
             "test_yosys_type/test_yosys_yowasp.rst",
-            "verilog/adder.v"
+            "code/verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
             "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
@@ -149,7 +149,7 @@ def test_yosys_system(self):
         TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
         TEST_FILES = [
             "test_yosys_type/test_yosys_system.rst",
-            "verilog/adder.v"
+            "code/verilog/adder.v"
         ]
         TEST_JINJA_DICT = {
             "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
@@ -171,7 +171,7 @@ def test_yosys_path(self):
         TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
         TEST_FILES = [
             "test_yosys_type/test_yosys_path.rst",
-            "verilog/adder.v"
+            "code/verilog/adder.v"
         ]
 
         yosys_path = shutil.which("yosys")
@@ -190,5 +190,57 @@ def test_yosys_path(self):
             app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
             app.build(force_all=True)
 
+class TestNMigen(TestBase):
+
+    TEST_CASE_NAME = "TestNMigen"
+    TEST_CASE_BUILD_DIR = os.path.join("build", TEST_CASE_NAME)
+
+    def test_yosys_script(self):
+        TEST_NAME = "test_nmigen"
+        TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
+        TEST_FILES = [
+            "test_nmigen/test_nmigen.rst",
+            "code/nmigen/counter.py"
+        ]
+        TEST_JINJA_DICT = {
+            "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
+            "master_doc": "'test_nmigen'",
+            "custom_variables": "''"
+        }
+
+        self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
+
+        # Run the Sphinx
+        sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
+        with docutils_namespace():
+            app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
+            app.build(force_all=True)
+
+class TestRTLIL(TestBase):
+
+    TEST_CASE_NAME = "TestRTLIL"
+    TEST_CASE_BUILD_DIR = os.path.join("build", TEST_CASE_NAME)
+
+    def test_yosys_script(self):
+        TEST_NAME = "test_rtlil"
+        TEST_BUILD_DIR = os.path.join("build", self.TEST_CASE_NAME, TEST_NAME)
+        TEST_FILES = [
+            "test_rtlil/test_rtlil.rst",
+            "code/rtlil/counter.il"
+        ]
+        TEST_JINJA_DICT = {
+            "hdl_diagrams_path": "'{}'".format(HDL_DIAGRAMS_PATH),
+            "master_doc": "'test_rtlil'",
+            "custom_variables": "''"
+        }
+
+        self.prepare_test(TEST_NAME, TEST_BUILD_DIR, TEST_FILES, **TEST_JINJA_DICT)
+
+        # Run the Sphinx
+        sphinx_dirs = get_sphinx_dirs(TEST_BUILD_DIR)
+        with docutils_namespace():
+            app = Sphinx(buildername="html", warningiserror=True, **sphinx_dirs)
+            app.build(force_all=True)
+
 if __name__ == '__main__':
     unittest.main()
diff --git a/tests/test_nmigen/test_nmigen.rst b/tests/test_nmigen/test_nmigen.rst
@@ -0,0 +1,37 @@
+Test nMigen
+===========
+
+This test checks diagram generation from nMigen sources.
+
+Yosys BlackBox Diagram
+----------------------
+
+.. code-block:: rst
+
+   .. hdl-diagram:: counter.py
+      :type: yosys-blackbox
+
+.. hdl-diagram:: counter.py
+   :type: yosys-blackbox
+
+Yosys AIG Diagram
+-----------------
+
+.. code-block:: rst
+
+   .. hdl-diagram:: counter.py
+      :type: yosys-aig
+
+.. hdl-diagram:: counter.py
+   :type: yosys-aig
+
+Netlistsvg Diagram
+------------------
+
+.. code-block:: rst
+
+   .. hdl-diagram:: counter.py
+      :type: netlistsvg
+
+.. hdl-diagram:: counter.py
+   :type: netlistsvg
diff --git a/tests/test_rtlil/test_rtlil.rst b/tests/test_rtlil/test_rtlil.rst
@@ -0,0 +1,37 @@
+Test RTLIL
+===========
+
+This test checks diagram generation from RTLIL sources.
+
+Yosys BlackBox Diagram
+----------------------
+
+.. code-block:: rst
+
+   .. hdl-diagram:: counter.il
+      :type: yosys-blackbox
+
+.. hdl-diagram:: counter.il
+   :type: yosys-blackbox
+
+Yosys AIG Diagram
+-----------------
+
+.. code-block:: rst
+
+   .. hdl-diagram:: counter.il
+      :type: yosys-aig
+
+.. hdl-diagram:: counter.il
+   :type: yosys-aig
+
+Netlistsvg Diagram
+------------------
+
+.. code-block:: rst
+
+   .. hdl-diagram:: counter.il
+      :type: netlistsvg
+
+.. hdl-diagram:: counter.il
+   :type: netlistsvg