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LATENCIES: solved latency problems in SimpleMemory memories. Even tho…
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…ugh, not working on Atomic: checking the wiki is not very clear if the latencies of memories work on atomic cpu
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Marcos Horro committed Oct 14, 2015
1 parent 82a527f commit 99f4c5e
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Showing 4 changed files with 26 additions and 4 deletions.
5 changes: 4 additions & 1 deletion configs/common/Options.py
Original file line number Diff line number Diff line change
Expand Up @@ -110,7 +110,10 @@ def addCommonOptions(parser):
parser.add_option("--spm-type-1", type="int", default=1)
parser.add_option("--spm-type-2", type="int", default=1)
parser.add_option("--spm-type-3", type="int", default=1)


parser.add_option("--spm-lat-1", type="string", default="10ns")
parser.add_option("--spm-lat-2", type="string", default="10ns")
parser.add_option("--spm-lat-3", type="string", default="10ns")

parser.add_option("-l", "--lpae", action="store_true")
parser.add_option("-V", "--virtualisation", action="store_true")
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18 changes: 18 additions & 0 deletions configs/common/ScratchPadConfig.py
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Expand Up @@ -46,8 +46,17 @@ def config_spm(options, system):
if (options.scratchpad >= 1):
addr_start = options.mem_size
for i in range (1, options.scratchpad+1):
# Getting attributes from options
spm_size = getattr(options, "spm_size_" + `i`)
spm_type = getattr(options, "spm_type_" + `i`)

#####################
# Choosing type of SPM:
# 1.- Inherits from SimpleMemory. Read latency 2ns and 1ns variable. BW=64GBs
# 2.- Inherits from SimpleMemory. Read latency 1ns. BW=128GBs
# 3.- Inherits from GDDR5. Modified front end and back end latencies
# 4.- Inherits from GDDR5. Lower latencies than GDDR5
######################
if (spm_type==1):
spm = ScratchpadMemory()
elif (spm_type==2):
Expand All @@ -56,8 +65,17 @@ def config_spm(options, system):
spm = ScratchpadMemoryDRAM()
else:
spm = ScratchpadMemoryDRAMLL()

# Needed to choose the range
spm.range = m5.objects.AddrRange(start = addr_start, size = spm_size)
# This is a hack. Be careful with it. If there are more spm, they will all be at the end
addr_start = spm.range.end + 1
# Just adding the latency: if SimpleMemory
if (spm_type==1)|(spm_type==2):
spm_lat = getattr(options, "spm_lat_" + `i`)
spm.latency = spm_lat
# Connecting to master bus
spm.port = system.membus.master
# Adding spm to the system
setattr(system, "spm_" + `i`, spm)

1 change: 1 addition & 0 deletions configs/spm/se.py
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# Marcos Horro Varela

# Simple test script
#
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6 changes: 3 additions & 3 deletions src/mem/ScratchpadMemory.py
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Expand Up @@ -44,7 +44,7 @@ class ScratchpadMemoryDRAM(GDDR5_4000_x64):
# by the queues only seeing the frontend contribution, and reads
# serviced by the memory seeing the sum of the two
# Basically: frontend -> reads; backend -> reads and writes
static_frontend_latency = Param.Latency("1ns", "Static frontend latency")
static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
static_backend_latency = Param.Latency("5ns", "Static backend latency")

# BASED ON DRAMCtrl (1300MHz) IMPLEMENTATION.
Expand All @@ -60,6 +60,6 @@ class ScratchpadMemoryDRAMLL(GDDR5_4000_x64):
# by the queues only seeing the frontend contribution, and reads
# serviced by the memory seeing the sum of the two
# Basically: frontend -> reads; backend -> reads and writes
static_frontend_latency = Param.Latency("5ns", "Static frontend latency")
static_backend_latency = Param.Latency("5ns", "Static backend latency")
static_frontend_latency = Param.Latency("4ns", "Static frontend latency")
static_backend_latency = Param.Latency("6ns", "Static backend latency")

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