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2020.1 unisims released under Apache 2.0
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202 changes: 202 additions & 0 deletions LICENSE
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5 changes: 5 additions & 0 deletions README.md
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# Xilinx Unisim Library

The Xilinx Unisim Library Verilog available as open source under Apache 2.0.

These files coincide with the 2020.1 release of Vivado.
97 changes: 97 additions & 0 deletions verilog/src/unisims/AND2B1L.v
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Two input AND gate implemented in place of a CLB Latch
// /___/ /\ Filename : AND2B1L.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 04/01/08 - Initial version.
// 04/14/09 - 517897 - Invert SRI not DI
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine
// 04/16/13 - 683925 - add invertible pin support.
// End Revision:
///////////////////////////////////////////////////////////////////////////////

`timescale 1 ps / 1 ps

`celldefine

module AND2B1L #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] IS_SRI_INVERTED = 1'b0
)(
output O,

input DI,
input SRI
);

// define constants
localparam MODULE_NAME = "AND2B1L";

reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "AND2B1L_dr.v"
`else
reg [0:0] IS_SRI_INVERTED_REG = IS_SRI_INVERTED;
`endif

`ifdef XIL_XECLIB
tri0 glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif

wire DI_in;
wire SRI_in;

assign DI_in = DI;
assign SRI_in = SRI ^ IS_SRI_INVERTED_REG;

`ifdef XIL_TIMING
reg notifier;
`endif

// begin behavioral model

assign O = ~glblGSR && DI_in && ~SRI_in;

// end behavioral model

`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(DI => O) = (0:0:0, 0:0:0);
(SRI => O) = (0:0:0, 0:0:0);
$width (negedge SRI, 0:0:0, 0, notifier);
$width (posedge SRI, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule

`endcelldefine
90 changes: 90 additions & 0 deletions verilog/src/unisims/AUTOBUF.v
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///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : AUTOBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision

`timescale 1 ps / 1 ps


`celldefine

module AUTOBUF (O, I);

parameter BUFFER_TYPE = "AUTO";

`ifdef XIL_TIMING

parameter LOC = "UNPLACED";

`endif


output O;

input I;

initial begin

case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase

end

buf B1 (O, I);

`ifdef XIL_TIMING

specify

(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;

endspecify

`endif

endmodule

`endcelldefine

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