Merge pull request #221 from YosysHQ/micko/fix_globals

Fix for global routing on XO2/XO3
YosysHQ · May 8, 2023 · f1e5710 · f1e5710
2 parents c99b22d + a53754a
commit f1e5710
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Showing 9 changed files with 24 additions and 11 deletions.
diff --git a/database b/database
diff --git a/fuzzers/machxo3/020-center-mux/6900/fuzzer.py b/fuzzers/machxo3/020-center-mux/6900/fuzzer.py
@@ -72,8 +72,8 @@ def fc_filter_dcc(a, n):
         # Thanks to fc_filter_dcc, make sure to manually connect DCC outputs to
         # entrance to global network!
         {
-            "netnames" : ["R13C19_VPRX0000", "R13C19_VPRX0100", "R13C19_VPRX0200", "R13C19_VPRX0300",
-                          "R13C19_VPRX0400", "R13C19_VPRX0500", "R13C19_VPRX0600", "R13C19_VPRX0700"],
+            "netnames" : ["R17C19_VPRX0000", "R17C19_VPRX0100", "R17C19_VPRX0200", "R17C19_VPRX0300",
+                          "R17C19_VPRX0400", "R17C19_VPRX0500", "R17C19_VPRX0600", "R17C19_VPRX0700"],
             "cfg" : FuzzConfig(job="GLOBAL_DCC_OUT", family="MachXO3", device="LCMXO3LF-6900C", ncl="center-mux.ncl",
                       tiles=["CENTER13:CENTER_EBR_CIB_4K", "CENTER_EBR29:CENTER_EBR",
                              "CENTER16:CENTER8", "CENTER15:CENTER7", "CENTER14:CENTER6",

diff --git a/fuzzers/machxo3/022-glb-cib_ebr/2100/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/2100/fuzzer.py
@@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids):
 
     # Up/Down conns
     ud_nets.extend(net_product(
-        net_product(["R6C{}_VPTX0{{}}00", "R11C{}_VPTX0{{}}00"], [tilepos[1]]),
+        net_product(["R5C{}_VPTX0{{}}00", "R11C{}_VPTX0{{}}00"], [tilepos[1]]),
         glb_ids))
 
     # Phantom DCCs- First fill in "T"/"B", and then global id
@@ -28,6 +28,8 @@ def flatten_nets(tilepos):
 jobs = [
     (FuzzConfig(job="CIB0_EBR0_END0_UPDOWN", family="MachXO3", device="LCMXO3LF-2100C", ncl="tap.ncl",
                       tiles=["CIB_R8C1:CIB_EBR_DUMMY_END3"]), flatten_nets((8,1))),
+    (FuzzConfig(job="CIB0_EBR2_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-2100C", ncl="tap.ncl",
+                      tiles=["CIB_R8C26:CIB_EBR2_END0"]), flatten_nets((8,26)))
 ]
 
 def main(args):

diff --git a/fuzzers/machxo3/022-glb-cib_ebr/4300/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/4300/fuzzer.py
@@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids):
 
     # Up/Down conns
     ud_nets.extend(net_product(
-        net_product(["R11C{}_VPTX0{{}}00", "R15C{}_VPTX0{{}}00"], [tilepos[1]]),
+        net_product(["R6C{}_VPTX0{{}}00", "R16C{}_VPTX0{{}}00"], [tilepos[1]]),
         glb_ids))
 
     # Phantom DCCs- First fill in "T"/"B", and then global id
@@ -27,7 +27,9 @@ def flatten_nets(tilepos):
 
 jobs = [
     (FuzzConfig(job="CIB_EBR0_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-4300C", ncl="tap.ncl",
-                      tiles=["CIB_R11C1:CIB_EBR0_END1"]), flatten_nets((11,1)))
+                      tiles=["CIB_R11C1:CIB_EBR0_END1"]), flatten_nets((11,1))),
+    (FuzzConfig(job="CIB0_EBR2_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-4300C", ncl="tap.ncl",
+                      tiles=["CIB_R11C32:CIB_EBR2_END1"]), flatten_nets((11,32)))
 
 ]
 

diff --git a/fuzzers/machxo3/022-glb-cib_ebr/6900/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/6900/fuzzer.py
@@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids):
 
     # Up/Down conns
     ud_nets.extend(net_product(
-        net_product(["R11C{}_VPTX0{{}}00", "R15C{}_VPTX0{{}}00"], [tilepos[1]]),
+        net_product(["R7C{}_VPTX0{{}}00", "R17C{}_VPTX0{{}}00", "R23C{}_VPTX0{{}}00"], [tilepos[1]]),
         glb_ids))
 
     # Phantom DCCs- First fill in "T"/"B", and then global id
@@ -26,6 +26,7 @@ def flatten_nets(tilepos):
     return [nets for netpair in [(0, 4), (1, 5), (2, 6), (3, 7)] for nets in mk_nets(tilepos, netpair)]
 
 jobs = [
+    #0
     (FuzzConfig(job="GLB_UPDOWN26", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl",
                       tiles=["CIB_R13C10:CIB_EBR0"]), mk_nets((13, 10), (2, 6))),
 
@@ -38,11 +39,11 @@ def flatten_nets(tilepos):
     (FuzzConfig(job="GLB_UPDOWN37", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl",
                       tiles=["CIB_R13C7:CIB_EBR0"]),  mk_nets((13, 7),  (3, 7))),
 
+    #4
     (FuzzConfig(job="CIB_EBR0_END2_DLL45_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl",
                       tiles=["CIB_R13C1:CIB_EBR0_END2_DLL45"]), flatten_nets((13,1))),
     (FuzzConfig(job="CIB_EBR2_END1_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl",
                       tiles=["CIB_R13C41:CIB_EBR2_END1"]), flatten_nets((13,41))),
-
     (FuzzConfig(job="CIB_EBR0_END2_DLL3_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl",
                       tiles=["CIB_R20C1:CIB_EBR0_END2_DLL3"]), flatten_nets((20,1))),
     (FuzzConfig(job="CIB_EBR2_END1_SP_UPDOWN", family="MachXO3", device="LCMXO3LF-6900C", ncl="tap.ncl",

diff --git a/fuzzers/machxo3/022-glb-cib_ebr/9400/fuzzer.py b/fuzzers/machxo3/022-glb-cib_ebr/9400/fuzzer.py
@@ -10,7 +10,7 @@ def mk_nets(tilepos, glb_ids):
 
     # Up/Down conns
     ud_nets.extend(net_product(
-        net_product(["R13C{}_VPTX0{{}}00", "R17C{}_VPTX0{{}}00"], [tilepos[1]]),
+        net_product(["R5C{}_VPTX0{{}}00", "R12C{}_VPTX0{{}}00", "R19C{}_VPTX0{{}}00", "R26C{}_VPTX0{{}}00"], [tilepos[1]]),
         glb_ids))
 
     # Phantom DCCs- First fill in "T"/"B", and then global id

diff --git a/libtrellis/include/RoutingGraph.hpp b/libtrellis/include/RoutingGraph.hpp
@@ -178,6 +178,7 @@ class RoutingGraph : public IdStore
     const MachXO2GlobalsInfo *global_data_machxo2;
     enum GlobalType {
         CENTER,
+        SPINE_LEFT_RIGHT,
         LEFT_RIGHT,
         UP_DOWN,
         BRANCH,

diff --git a/libtrellis/src/RoutingGraph.cpp b/libtrellis/src/RoutingGraph.cpp
@@ -378,6 +378,12 @@ RoutingId RoutingGraph::find_machxo2_global_position(int row, int col, const std
         curr_global.loc.y = center.first;
         return curr_global;
 
+    } else if(strategy == GlobalType::SPINE_LEFT_RIGHT) {
+        assert(row == spine_1.row || row == spine_2.row);
+        curr_global.id = ident(db_name);
+        curr_global.loc.x = center.second;
+        curr_global.loc.y = row;
+        return curr_global;
     // If we found a global emanating from the CENTER MUX, return a L_/R_
     // global net in the center tile based upon the current tile position
     // (specifically column).
@@ -582,11 +588,12 @@ RoutingGraph::GlobalType RoutingGraph::get_global_type_from_name(const std::stri
     // static const std::regex qsw90(R"(G_DQSW90)", std::regex::optimize);
 
     if(regex_match(db_name, match, global_entry) ||
-        regex_match(db_name, match, global_left_right) ||
         regex_match(db_name, match, center_mux_glb_out) ||
         regex_match(db_name, match, cib_out_to_glb) ||
         regex_match(db_name, match, dcm_sig)) {
         return GlobalType::CENTER;
+    } else if(regex_match(db_name, match, global_left_right)) {
+        return GlobalType::SPINE_LEFT_RIGHT;
     } else if(regex_match(db_name, match, global_left_right_g)) {
         return GlobalType::LEFT_RIGHT;
     } else if(regex_match(db_name, match, global_up_down) ||

diff --git a/libtrellis/src/Tile.cpp b/libtrellis/src/Tile.cpp
@@ -41,7 +41,7 @@ map<pair<int, int>, pair<int, int>> center_map = {
     // LCMXO2-4000, LCMXO3-4300
     {make_pair(22, 31), make_pair(11, 15)},
     // LCMXO2-7000, LCMXO3-6900
-    {make_pair(27, 40), make_pair(13, 18)},
+    {make_pair(27, 40), make_pair(17, 18)},
     // LCMXO3-9400
     {make_pair(31, 48), make_pair(15, 24)},
 };