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Support for multi-line string for system verilog #4871

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KelvinChung2000 opened this issue Jan 28, 2025 · 0 comments

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feature-request SystemVerilog

KelvinChung2000 commented Jan 28, 2025

Feature Description

In the System Verilog Specification chapter 5.9 stated:

A string literal shall be contained in a single line unless the newline character is immediately preceded by a
\ (backslash). In this case, the backslash and the newline character are ignored. There is no predefined limit
to the length of a string literal.

I would like to have support for this, mainly to aid the readability of very long attribute strings.

KelvinChung2000 added the feature-request label

KrystalDelusion added the SystemVerilog label

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