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read_liberty incorrectly models a latch with 'clear' input #4885

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povik opened this issue Feb 7, 2025 · 0 comments · May be fixed by #4907
Open

read_liberty incorrectly models a latch with 'clear' input #4885

povik opened this issue Feb 7, 2025 · 0 comments · May be fixed by #4907
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bug fix pending PR with a fix is pending

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@povik
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povik commented Feb 7, 2025

Version

Yosys 0.49+21 (git sha1 772b9c0, clang++ 11.1.0 -fPIC -O3)

On which OS did this happen?

macOS

Reproduction Steps

Load sg13g2_dllrq_1 from the ihp-sg13g2 PDK, the elaborated circuit is

Image

Expected Behavior

Circuit models the cell correctly

Actual Behavior

D input is incorrectly ignored
@povik povik added the pending-verification This issue is pending verification and/or reproduction label Feb 7, 2025
@widlarizer widlarizer linked a pull request Feb 17, 2025 that will close this issue
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@widlarizer widlarizer added bug fix pending PR with a fix is pending and removed pending-verification This issue is pending verification and/or reproduction labels Feb 17, 2025
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liberty: fix clear and preset latches YosysHQ/yosys
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@povik @widlarizer