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liberty: fix clear and preset latches #4907

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liberty: fix clear and preset latches #4907

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Fixes #4885. Currently, all Liberty-described clear and preset latches were modeled with a disconnected data input, since the enable logic is clobbering the data signal. This PR fixes this.

Reproducer, from IHP 130:

library (sg13g2_stdcell_fast_1p32V_m40C_latch_repro) {
  comment : "IHP Microelectronics GmbH, 2024, modified";
  date : "$Date: Thu Mar 14 15:30:46 2024 $";
  revision : "$Revision: 0.1.0 $";
  cell (sg13g2_dllrq_1) {
    area : 29.0304;
    pin (Q) {
      direction : "output";
      function : "IQ";
    }
    pin (D) {
      direction : "input";
    }
    pin (GATE_N) {
      clock : true;
      direction : "input";
    }
    pin (RESET_B) {
      direction : "input";
    }
    latch (IQ,IQN) {
      clear : "RESET_B'";
      data_in : "D";
      enable : "GATE_N'";
    }
  }
}

yosys -p "read_liberty latch.lib; opt; show reproduces the image
yosys -p "read_liberty latch.lib; show shows that some attempt to use D is made

@widlarizer widlarizer requested a review from povik February 17, 2025 16:44
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read_liberty incorrectly models a latch with 'clear' input
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@widlarizer