Continuous assign drives right-hand side

[rantvm]

Version

Yosys 0.49+29 (git sha1 ce5ad2a, clang++ 18.1.8 -fPIC -O3)

On which OS did this happen?

Linux

Reproduction Steps

The following Verilog exhibits the unexpected behaviour. Note, in particular, that top.first_delay is only present on the right-hand side of a continuous assign.

module top
(
  input wire clock,
  input wire signal,
  output wire first_delay,
  output wire second_delay
);

  wire delay;
  dff dff1(clock, signal, delay);
  dff dff2(clock, delay, second_delay);
  
  assign second_delay = first_delay;
endmodule


module dff
(
  input wire c,
  input wire d,
  output reg q
);

  always @(posedge c)
    q <= d;

endmodule

Then synthesize using yosys -p 'read_verilog top.v; synth; show top'

Expected Behavior

top.first_delay should float. Diagnostic should be issued for top.second_delay being doubly-driven.

Actual Behavior

top.second_delay is driven onto top.first_delay. No diagnostic is issued.

Synthesis result illustrated in the following diagram produced by show -format svg top.