update kernel to mainline 6.5

kernel_patches/arm64-sm8250/0001-drm-msm-dpu1-improve-support-for-active-CTLs.patch

@@ -0,0 +1,84 @@
+From 632cb3280b004f88b7230f7d71237be96e8b4578 Mon Sep 17 00:00:00 2001
+From: Dmitry Baryshkov <[email protected]>
+Date: Sun, 14 Mar 2021 04:52:34 +0300
+Subject: [PATCH 01/21] drm/msm/dpu1: improve support for active CTLs
+
+- Support setting master interface if several INTFs are to be handled by
+  a single CTL
+
+- Support setting handling several MERGE_3D instances using a single
+  CTL.
+
+Signed-off-by: Dmitry Baryshkov <[email protected]>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 15 +++++++++++++++
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h |  2 ++
+ 2 files changed, 17 insertions(+)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+index bbdc95ce374a..308c50ebe07a 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+@@ -511,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
+ 	u32 intf_active = 0;
+ 	u32 wb_active = 0;
+ 	u32 mode_sel = 0;
++	u32 merge_3d_active = 0;
+
+ 	/* CTL_TOP[31:28] carries group_id to collate CTL paths
+ 	 * per VM. Explicitly disable it until VM support is
+@@ -534,10 +535,17 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
+ 	if (cfg->wb)
+ 		wb_active |= BIT(cfg->wb - WB_0);
+
++	merge_3d_active = DPU_REG_READ(c, CTL_MERGE_3D_ACTIVE);
++	if (cfg->merge_3d)
++		merge_3d_active |= BIT(cfg->merge_3d - MERGE_3D_0);
++
+ 	DPU_REG_WRITE(c, CTL_TOP, mode_sel);
+ 	DPU_REG_WRITE(c, CTL_INTF_ACTIVE, intf_active);
+ 	DPU_REG_WRITE(c, CTL_WB_ACTIVE, wb_active);
+
++	if (cfg->intf_master)
++		DPU_REG_WRITE(c, CTL_INTF_MASTER, BIT(cfg->intf_master - INTF_0));
++
+ 	if (cfg->merge_3d)
+ 		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
+ 			      BIT(cfg->merge_3d - MERGE_3D_0));
+@@ -545,6 +553,13 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
+
+ 	if (cfg->dsc)
+ 		DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
++	if (cfg->merge_3d)
++		DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
++
++	if (cfg->intf_master)
++		DPU_DEBUG_DRIVER("ACTIVE: %x %x %lx\n", intf_active, merge_3d_active, BIT(cfg->intf_master - INTF_0));
++	else
++		DPU_DEBUG_DRIVER("ACTIVE: %x %x\n", intf_active, merge_3d_active);
+ }
+
+ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+index 78611a831697..266113cb2270 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+@@ -36,6 +36,7 @@ struct dpu_hw_stage_cfg {
+ /**
+  * struct dpu_hw_intf_cfg :Describes how the DPU writes data to output interface
+  * @intf :                 Interface id
++ * @intf_master:           Master interface id in the dual pipe topology
+  * @mode_3d:               3d mux configuration
+  * @merge_3d:              3d merge block used
+  * @intf_mode_sel:         Interface mode, cmd / vid
+@@ -44,6 +45,7 @@ struct dpu_hw_stage_cfg {
+  */
+ struct dpu_hw_intf_cfg {
+ 	enum dpu_intf intf;
++	enum dpu_intf intf_master;
+ 	enum dpu_wb wb;
+ 	enum dpu_3d_blend_mode mode_3d;
+ 	enum dpu_merge_3d merge_3d;
+-- 
+2.14.3
+

kernel_patches/arm64-sm8250/0002-drm-msm-dpu1-use-one-active-CTL-if-it-is-available.patch

@@ -0,0 +1,136 @@
+From 1ca725e2b24b5118ace7f60e3dce8e1774dd583d Mon Sep 17 00:00:00 2001
+From: Dmitry Baryshkov <[email protected]>
+Date: Sun, 14 Mar 2021 04:58:32 +0300
+Subject: [PATCH 02/21] drm/msm/dpu1: use one active CTL if it is available
+
+Unlike previous generation, with newer ("active") CTLs it is possible to
+use just one CTL to handle both interfaces. And one has to use single
+CTL to support master/slave DSI config. So use one active CTL if it is
+available.
+
+Signed-off-by: Dmitry Baryshkov <[email protected]>
+---
+ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h |  1 +
+ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h |  1 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c            |  8 ++++++--
+ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h         |  1 +
+ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c                 | 14 ++++++++++----
+ drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h                 |  1 +
+ 6 files changed, 20 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+index 282d410269ff..e403ed846edd 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+@@ -15,6 +15,7 @@ static const struct dpu_caps sm8150_dpu_caps = {
+ 	.has_dim_layer = true,
+ 	.has_idle_pc = true,
+ 	.has_3d_merge = true,
++	.has_active_ctls = true,
+ 	.max_linewidth = 4096,
+ 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+index 2c40229ea515..0261c8d8c1c9 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
++++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+@@ -15,6 +15,7 @@ static const struct dpu_caps sm8250_dpu_caps = {
+ 	.has_dim_layer = true,
+ 	.has_idle_pc = true,
+ 	.has_3d_merge = true,
++	.has_active_ctls = true,
+ 	.max_linewidth = 4096,
+ 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+ };
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+index 1dc5dbe58572..31656eb0e7a4 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+@@ -1095,14 +1095,18 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
+ 			return;
+ 		}
+
+-		if (!hw_ctl[i]) {
++		/* Use first (and only) CTL if active CTLs are supported */
++		if (dpu_kms->catalog->caps->has_active_ctls)
++			phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[0]);
++		else
++			phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
++		if (!phys->hw_ctl) {
+ 			DPU_ERROR_ENC(dpu_enc,
+ 				"no ctl block assigned at idx: %d\n", i);
+ 			return;
+ 		}
+
+ 		phys->hw_pp = dpu_enc->hw_pp[i];
+-		phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);
+
+ 		phys->cached_mode = crtc_state->adjusted_mode;
+ 		if (phys->ops.atomic_mode_set)
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+index 71584cd56fd7..bc421ef403a0 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+@@ -375,6 +375,7 @@ struct dpu_caps {
+ 	bool has_dim_layer;
+ 	bool has_idle_pc;
+ 	bool has_3d_merge;
++	bool has_active_ctls;
+ 	/* SSPP limits */
+ 	u32 max_linewidth;
+ 	u32 pixel_ram_size;
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+index f4dda88a73f7..29aec4b7f5b0 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+@@ -228,6 +228,7 @@ int dpu_rm_init(struct dpu_rm *rm,
+ 		}
+ 		rm->ctl_blks[ctl->id - CTL_0] = &hw->base;
+ 	}
++	rm->has_active_ctls = cat->caps->has_active_ctls;
+
+ 	for (i = 0; i < cat->dspp_count; i++) {
+ 		struct dpu_hw_dspp *hw;
+@@ -465,10 +466,15 @@ static int _dpu_rm_reserve_ctls(
+ 	int i = 0, j, num_ctls;
+ 	bool needs_split_display;
+
+-	/* each hw_intf needs its own hw_ctrl to program its control path */
+-	num_ctls = top->num_intf;
++	if (rm->has_active_ctls) {
++		num_ctls = 1;
++		needs_split_display = false;
++	} else {
++		/* each hw_intf needs its own hw_ctrl to program its control path */
++		num_ctls = top->num_intf;
+
+-	needs_split_display = _dpu_rm_needs_split_display(top);
++		needs_split_display = _dpu_rm_needs_split_display(top);
++	}
+
+ 	for (j = 0; j < ARRAY_SIZE(rm->ctl_blks); j++) {
+ 		const struct dpu_hw_ctl *ctl;
+@@ -486,7 +492,7 @@ static int _dpu_rm_reserve_ctls(
+
+ 		DPU_DEBUG("ctl %d caps 0x%lX\n", j + CTL_0, features);
+
+-		if (needs_split_display != has_split_display)
++		if (!rm->has_active_ctls && needs_split_display != has_split_display)
+ 			continue;
+
+ 		ctl_idx[i] = j;
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+index d62c2edb2460..d1b55482b8b1 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+@@ -33,6 +33,7 @@ struct dpu_rm {
+ 	struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
+ 	struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
+ 	struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
++	bool has_active_ctls;
+ };
+
+ /**
+-- 
+2.14.3
+

kernel_patches/arm64-sm8250/0003-drm-msm-dpu1-dpu_encoder_phys_-proper-suppor-for-act.patch

@@ -0,0 +1,54 @@
+From 5334dcb0f34ba6e8bbfef4745ce62f1c341aa9d1 Mon Sep 17 00:00:00 2001
+From: Dmitry Baryshkov <[email protected]>
+Date: Sun, 14 Mar 2021 05:03:35 +0300
+Subject: [PATCH 03/21] drm/msm/dpu1: dpu_encoder_phys_*: proper suppor for
+ active CTLs
+
+Adapt dpu_encoder_phys_* to properly support active CTLs and their
+features.
+
+Signed-off-by: Dmitry Baryshkov <[email protected]>
+---
+ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 ++
+ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 5 ++++-
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+index 74470d068622..f6bd2a88d548 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+@@ -60,6 +60,8 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
+ 		return;
+
+ 	intf_cfg.intf = phys_enc->hw_intf->idx;
++	if (phys_enc->split_role == ENC_ROLE_MASTER)
++		intf_cfg.intf_master = phys_enc->hw_intf->idx;
+ 	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
+ 	intf_cfg.stream_sel = cmd_enc->stream_sel;
+ 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+index 3a374292f311..b5549cab9902 100644
+--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
++++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+@@ -271,6 +271,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
+ 	DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc);
+
+ 	intf_cfg.intf = phys_enc->hw_intf->idx;
++	if (phys_enc->split_role == ENC_ROLE_MASTER)
++		intf_cfg.intf_master = phys_enc->hw_intf->idx;
+ 	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
+ 	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
+ 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+@@ -345,7 +347,8 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
+ static bool dpu_encoder_phys_vid_needs_single_flush(
+ 		struct dpu_encoder_phys *phys_enc)
+ {
+-	return phys_enc->split_role != ENC_ROLE_SOLO;
++	return !(phys_enc->hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) &&
++		phys_enc->split_role != ENC_ROLE_SOLO;
+ }
+
+ static void dpu_encoder_phys_vid_atomic_mode_set(
+-- 
+2.14.3
+

kernel_patches/arm64-sm8250/0004-dt-bindings-mfd-qcom-qca639x-add-binding-for-QCA639x.patch

@@ -0,0 +1,110 @@
+From d100cde0eecc6ce794f609bac7f3a724c5c2c2e0 Mon Sep 17 00:00:00 2001
+From: Dmitry Baryshkov <[email protected]>
+Date: Sun, 20 Dec 2020 18:47:57 +0300
+Subject: [PATCH 04/21] dt-bindings: mfd: qcom,qca639x: add binding for QCA639x
+ defvice
+
+Qualcomm QCA639x is a family of WiFi + Bluetooth SoCs, with BT part
+being controlled through the UART and WiFi being present on PCIe bus.
+Both blocks share common power sources. Add binding to describe power
+sequencing required to power up this device.
+
+Signed-off-by: Dmitry Baryshkov <[email protected]>
+---
+ .../devicetree/bindings/mfd/qcom,qca639x.yaml      | 84 ++++++++++++++++++++++
+ 1 file changed, 84 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml
+
+diff --git a/Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml b/Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml
+new file mode 100644
+index 000000000000..d43c75da136f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mfd/qcom,qca639x.yaml
+@@ -0,0 +1,84 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: "http://devicetree.org/schemas/mfd/qcom,qca639x.yaml#"
++$schema: "http://devicetree.org/meta-schemas/core.yaml#"
++
++title: Qualcomm QCA639x WiFi + Bluetoot SoC bindings
++
++maintainers:
++  - Andy Gross <[email protected]>
++  - Bjorn Andersson <[email protected]>
++
++description: |
++  This binding describes thes Qualcomm QCA6390 or QCA6391 power supplies and
++  enablement pins.
++
++properties:
++  compatible:
++    const: qcom,qca639x
++
++  '#power-domain-cells':
++    const: 0
++
++  pinctrl-0: true
++  pinctrl-1: true
++
++  pinctrl-names:
++    items:
++      - const: default
++      - const: active
++
++  vddaon-supply:
++    description:
++      0.95V always-on LDO power input
++
++  vddpmu-supply:
++    description:
++      0.95V LDO power input to PMU
++
++  vddrfa1-supply:
++    description:
++      0.95V LDO power input to RFA
++
++  vddrfa2-supply:
++    description:
++      1.25V LDO power input to RFA
++
++  vddrfa3-supply:
++    description:
++      2V LDO power input to RFA
++
++  vddpcie1-supply:
++    description:
++      1.25V LDO power input to PCIe part
++
++  vddpcie2-supply:
++    description:
++      2V LDO power input to PCIe part
++
++  vddio-supply:
++    description:
++      1.8V VIO input
++
++additionalProperties: false
++
++examples:
++  - |
++    qca639x: qca639x {
++      compatible = "qcom,qca639x";
++      #power-domain-cells = <0>;
++
++      vddaon-supply = <&vreg_s6a_0p95>;
++      vddpmu-supply = <&vreg_s2f_0p95>;
++      vddrfa1-supply = <&vreg_s2f_0p95>;
++      vddrfa2-supply = <&vreg_s8c_1p3>;
++      vddrfa3-supply = <&vreg_s5a_1p9>;
++      vddpcie1-supply = <&vreg_s8c_1p3>;
++      vddpcie2-supply = <&vreg_s5a_1p9>;
++      vddio-supply = <&vreg_s4a_1p8>;
++      pinctrl-names = "default", "active";
++      pinctrl-0 = <&wlan_default_state &bt_default_state>;
++      pinctrl-1 = <&wlan_active_state &bt_active_state>;
++    };
++...
+-- 
+2.14.3
+