TMCL-Interface: Fix the default for the default_register_address_bit_…

…width
analogdevicesinc · Jan 31, 2025 · 5dd724f · 5dd724f
1 parent b9f95a2
commit 5dd724f
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/pytrinamic/connections/tmcl_interface.py b/pytrinamic/connections/tmcl_interface.py
@@ -31,7 +31,7 @@ class TmclInterface(ABC):
 
     """
 
-    def __init__(self, host_id=2, default_module_id=1, default_ap_index_bit_width=8, default_register_address_bit_width=10):
+    def __init__(self, host_id=2, default_module_id=1, default_ap_index_bit_width=8, default_register_address_bit_width=12):
         """
         :param int host_id: The ID of the TMCL host. This ID is the same for each module
             when communicating with multiple modules.