General updates:

- Added/Updated licensce headers - Updated testbench depndencies - Updated class hierarchy Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
analogdevicesinc · Jan 27, 2025 · 7800758 · 7800758
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diff --git a/library/drivers/common/scoreboard.sv b/library/drivers/common/scoreboard.sv
@@ -1,3 +1,38 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
 `include "utils.svh"
 
 package scoreboard_pkg;

diff --git a/library/drivers/common/scoreboard_pack.sv b/library/drivers/common/scoreboard_pack.sv
@@ -1,3 +1,38 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsabilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
 `include "utils.svh"
 
 package scoreboard_pack_pkg;
@@ -49,50 +84,6 @@ package scoreboard_pack_pkg;
 
       if (this.enabled == 0)
         return;
-
-      // forever begin : tx_path
-      //   if (this.enabled == 0)
-      //     break;
-      //   if ((this.source_byte_stream_size > 0) &&
-      //         (this.sink_byte_stream_size >= this.channels*this.samples*this.width/8)) begin
-      //     byte_streams_empty_sig = 0;
-      //     for (int i=0; i<this.channels*this.samples*this.width/8; i++) begin
-      //       sink_byte_stream_block[i] = this.sink_byte_stream.pop_back();
-      //       this.sink_byte_stream_size--;
-      //     end
-      //     for (int i=0; i<outer_loop; i++) begin
-      //       for (int j=0; j<inner_loop; j++) begin
-      //         for (int k=0; k<this.width/8; k++) begin
-      //           source_byte = this.source_byte_stream.pop_back();
-      //           if (this.sink_type == CYCLIC)
-      //             this.source_byte_stream.push_front(source_byte);
-      //           else
-      //             this.source_byte_stream_size--;
-      //           sink_byte = sink_byte_stream_block[(outer_loop*j+i)*this.width/8+k];
-      //           this.info($sformatf("Scoreboard source-sink data: exp %h - rcv %h", source_byte, sink_byte), 100);
-      //           if (source_byte != sink_byte) begin
-      //             this.error($sformatf("Scoreboard failed at: exp %h - rcv %h", source_byte, sink_byte));
-      //           end
-      //         end
-      //       end
-      //     end
-      //   end else begin
-      //     if ((this.source_byte_stream_size == 0) &&
-      //         (this.sink_byte_stream_size == 0)) begin
-      //       byte_streams_empty_sig = 1;
-      //       ->>byte_streams_empty;
-      //     end
-      //     fork begin
-      //       fork
-      //         @source_transaction_event;
-      //         @sink_transaction_event;
-      //         @stop_scoreboard;
-      //       join_any
-      //       byte_streams_empty_sig = 0;
-      //       disable fork;
-      //     end join
-      //   end
-      // end
 
       while ((this.subscriber_source.get_size() > 0) &&
             (this.subscriber_sink.get_size() >= this.channels*this.samples*this.width/8)) begin

diff --git a/library/drivers/common/watchdog.sv b/library/drivers/common/watchdog.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,12 +26,13 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
 // ***************************************************************************
 // ***************************************************************************
+
 `include "utils.svh"
 
 package watchdog_pkg;

diff --git a/library/drivers/data_offload/data_offload_api.sv b/library/drivers/data_offload/data_offload_api.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2024 - 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -38,19 +38,20 @@
 package data_offload_api_pkg;
 
   import logger_pkg::*;
-  import adi_peripheral_pkg::*;
-  import adi_regmap_data_offload_pkg::*;
+  import adi_common_pkg::*;
+  import adi_api_pkg::*;
   import adi_regmap_pkg::*;
-  import reg_accessor_pkg::*;
+  import adi_regmap_data_offload_pkg::*;
+  import m_axi_sequencer_pkg::*;
 
-  class data_offload_api extends adi_peripheral;
+  class data_offload_api extends adi_api;
 
     // -----------------
     //
     // -----------------
     function new(
       input string name,
-      input reg_accessor bus,
+      input m_axi_sequencer_base bus,
       input bit [31:0] base_address,
       input adi_component parent = null);
 

diff --git a/library/drivers/dmac/dma_trans.sv b/library/drivers/dmac/dma_trans.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014 - 2018, 2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //

diff --git a/library/drivers/dmac/dmac_api.sv b/library/drivers/dmac/dmac_api.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2018, 2024 (c) Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014 - 2018, 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -38,13 +38,14 @@
 package dmac_api_pkg;
 
   import logger_pkg::*;
-  import adi_peripheral_pkg::*;
-  import adi_regmap_dmac_pkg::*;
+  import adi_common_pkg::*;
+  import adi_api_pkg::*;
   import adi_regmap_pkg::*;
-  import reg_accessor_pkg::*;
+  import adi_regmap_dmac_pkg::*;
+  import m_axi_sequencer_pkg::*;
   import dma_trans_pkg::*;
 
-  class dmac_api extends adi_peripheral;
+  class dmac_api extends adi_api;
 
     // DMAC parameters
     axi_dmac_params_t p;
@@ -54,7 +55,7 @@ package dmac_api_pkg;
     // -----------------
     function new(
       input string name,
-      input reg_accessor bus,
+      input m_axi_sequencer_base bus,
       input bit [31:0] base_address,
       input adi_component parent = null);
 

diff --git a/library/drivers/jesd/adi_jesd204_pkg.sv b/library/drivers/jesd/adi_jesd204_pkg.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,19 +26,21 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
 // ***************************************************************************
 // ***************************************************************************
+
 `include "utils.svh"
 
 package adi_jesd204_pkg;
 
   import logger_pkg::*;
-  import adi_peripheral_pkg::*;
-  import reg_accessor_pkg::*;
+  import adi_common_pkg::*;
+  import adi_api_pkg::*;
+  import m_axi_sequencer_pkg::*;
   import adi_regmap_pkg::*;
   import adi_regmap_jesd_tx_pkg::*;
   import adi_regmap_jesd_rx_pkg::*;
@@ -181,7 +183,7 @@ package adi_jesd204_pkg;
   //============================================================================
   // Base Link layer class
   //============================================================================
-  class link_layer extends adi_peripheral;
+  class link_layer extends adi_api;
 
     jesd_link link;
     int dp_width = 4;  // Data width towards Phy
@@ -196,7 +198,7 @@ package adi_jesd204_pkg;
     // -----------------
     //
     // -----------------
-    function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link);
+    function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link);
 
       super.new(name, bus, base_address);
       this.link = link;
@@ -273,7 +275,7 @@ package adi_jesd204_pkg;
     // -----------------
     //
     // -----------------
-    function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link);
+    function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link);
       super.new(name, bus, base_address, link);
     endfunction
 
@@ -433,7 +435,7 @@ package adi_jesd204_pkg;
     // -----------------
     //
     // -----------------
-    function new (string name, reg_accessor bus, bit [31:0] base_address, jesd_link link);
+    function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address, jesd_link link);
       super.new(name, bus, base_address, link);
     endfunction
 

diff --git a/library/drivers/xcvr/adi_xcvr_pkg.sv b/library/drivers/xcvr/adi_xcvr_pkg.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright 2014 - 2021 (c) Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014 - 2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,22 +26,23 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on_line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
 // ***************************************************************************
 // ***************************************************************************
+
 `include "utils.svh"
 
 package adi_xcvr_pkg;
 
   import logger_pkg::*;
-  import adi_peripheral_pkg::*;
-  import reg_accessor_pkg::*;
+  import adi_common_pkg::*;
+  import adi_api_pkg::*;
+  import m_axi_sequencer_pkg::*;
   import adi_regmap_pkg::*;
   import adi_regmap_xcvr_pkg::*;
-  import adi_jesd204_pkg::*;
 
   typedef enum bit [2:0] {
     OUTCLKPCS = 1,
@@ -285,7 +286,7 @@ package adi_xcvr_pkg;
   //============================================================================
   // Xilinx XCVR class
   //============================================================================
-  class xcvr extends adi_peripheral;
+  class xcvr extends adi_api;
 
     // Capabilities
     bit qpll_enable;
@@ -299,7 +300,7 @@ package adi_xcvr_pkg;
     // -----------------
     //
     // -----------------
-    function new (string name, reg_accessor bus, bit [31:0] base_address);
+    function new (string name, m_axi_sequencer_base bus, bit [31:0] base_address);
       super.new(name, bus, base_address);
     endfunction
 

diff --git a/library/includes/Makeinclude_axi.mk b/library/includes/Makeinclude_axi.mk
@@ -1,4 +1,4 @@
-## Copyright 2024(c) Analog Devices, Inc.
+## Copyright (C) 2024 - 2025 Analog Devices, Inc.
 ####################################################################################
 ####################################################################################
 
@@ -9,4 +9,3 @@ SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/s_axi_sequencer.sv
 SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/adi_axi_monitor.sv
 SV_DEPS += $(TB_LIBRARY_PATH)/vip/amd/axi/axi_definitions.svh
 SV_DEPS += $(TB_LIBRARY_PATH)/utilities/pub_sub_pkg.sv
-SV_DEPS += $(TB_LIBRARY_PATH)/regmaps/reg_accessor.sv
diff --git a/library/includes/Makeinclude_axis.mk b/library/includes/Makeinclude_axis.mk
@@ -1,4 +1,4 @@
-## Copyright 2024(c) Analog Devices, Inc.
+## Copyright (C) 2024 Analog Devices, Inc.
 ####################################################################################
 ####################################################################################